| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | Allow constant function calls in for loops and generate if and case | Zachary Snow | 2020-06-29 | 2 | -0/+76 | |
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| * / | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 1 | -1/+1 | |
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| * | Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve | Eddie Hung | 2020-06-04 | 1 | -1/+2 | |
| |\ | | | | | abc9: -dff improvements | |||||
| | * | abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ | Eddie Hung | 2020-05-29 | 1 | -1/+2 | |
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| * | | Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings | Eddie Hung | 2020-06-03 | 3 | -4/+4 | |
| |\ \ | | | | | | | tests: reduce test warnings | |||||
| | * | | tests: fix some test warnings | Eddie Hung | 2020-05-25 | 3 | -4/+4 | |
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| * / | printattrs: Add test. | Alberto Gonzalez | 2020-05-27 | 1 | -0/+14 | |
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| * | xaiger: add testcase | Eddie Hung | 2020-05-24 | 1 | -0/+13 | |
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| * | abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it | Eddie Hung | 2020-05-14 | 1 | -3/+8 | |
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| * | abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ | Eddie Hung | 2020-05-14 | 1 | -2/+21 | |
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| * | abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too | Eddie Hung | 2020-05-14 | 1 | -5/+7 | |
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| * | Merge pull request #2028 from zachjs/master | Eddie Hung | 2020-05-06 | 2 | -0/+17 | |
| |\ | | | | | verilog: allow null gen-if then block | |||||
| | * | verilog: allow null gen-if then block | Zachary Snow | 2020-05-06 | 2 | -0/+17 | |
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| * | | Merge pull request #2024 from YosysHQ/eddie/primitive_src | Eddie Hung | 2020-05-05 | 1 | -0/+16 | |
| |\ \ | | | | | | | verilog: set src attribute for primitives | |||||
| | * | | tests: add tests for primitives' src | Eddie Hung | 2020-05-04 | 1 | -0/+16 | |
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| * / | verilog: fix specify src attribute | Eddie Hung | 2020-05-04 | 1 | -0/+6 | |
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| * | test: add test for #2014 | Eddie Hung | 2020-05-02 | 1 | -0/+12 | |
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| * | Merge pull request #1973 from YosysHQ/eddie/fix1966 | Eddie Hung | 2020-04-22 | 1 | -1/+3 | |
| |\ | | | | | tests: fix various/plugin.sh when PREFIX != /usr/local/share | |||||
| | * | tests: use `yosys-config --datdir` instead of hard-coded | Eddie Hung | 2020-04-22 | 1 | -1/+3 | |
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| * | | Merge pull request #1950 from YosysHQ/eddie/design_import | Eddie Hung | 2020-04-22 | 2 | -5/+22 | |
| |\ \ | | | | | | | design: -import to not count black/white-boxes as candidates for top | |||||
| | * | | design: add test | Eddie Hung | 2020-04-16 | 2 | -5/+22 | |
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| * | | Merge pull request #1976 from YosysHQ/dave/fix-sim-const | Claire Wolf | 2020-04-22 | 1 | -0/+13 | |
| |\ \ | | | | | | | sim: Fix handling of constant-connected cell inputs at startup | |||||
| | * | | sim: Fix handling of constant-connected cell inputs at startup | David Shah | 2020-04-21 | 1 | -0/+13 | |
| | |/ | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | hierarchy: Convert positional parameters to named. | Marcelina Kościelnicka | 2020-04-21 | 1 | -0/+23 | |
| | | | | | | | | | Fixes #1821. | |||||
| * | | Merge pull request #1851 from YosysHQ/claire/bitselwrite | Claire Wolf | 2020-04-21 | 13 | -0/+1224 | |
| |\ \ | | | | | | | Improved rewrite code for writing to bit slice | |||||
| | * | | Remove '-ignore_unknown_cells' option from 'sat' | Eddie Hung | 2020-04-20 | 1 | -6/+6 | |
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| | * | | Simplify test case script | Eddie Hung | 2020-04-20 | 1 | -30/+17 | |
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| | * | | Modifications of tests as per Eddie's request | diego | 2020-04-20 | 13 | -0/+1237 | |
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| * | | | abc9: add testcase reduced from #1970 | Eddie Hung | 2020-04-20 | 1 | -0/+19 | |
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| * | | tests: add design -delete tests | Eddie Hung | 2020-04-16 | 2 | -0/+18 | |
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| * | | ast: Fix handling of identifiers in the global scope | David Shah | 2020-04-16 | 1 | -0/+18 | |
| |/ | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | tests: add testcases from #1876 | Eddie Hung | 2020-04-14 | 1 | -0/+60 | |
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| * | tests: add a quick plugin test | Eddie Hung | 2020-04-09 | 3 | -0/+22 | |
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| * | Add support for SystemVerilog-style `define to Verilog frontend | Rupert Swarbrick | 2020-03-27 | 4 | -0/+50 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly. | |||||
| * | Add test for abc9+mince issue | David Shah | 2020-03-20 | 1 | -0/+17 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | fsm_extract: Initialize celltypes with full design. | Marcin Kościelnicki | 2020-03-19 | 1 | -0/+33 | |
| | | | | | Fixes #1781. | |||||
| * | Add test for `exec` command. | Alberto Gonzalez | 2020-03-16 | 1 | -0/+6 | |
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| * | Merge pull request #1759 from zeldin/constant_with_comment_redux | Miodrag Milanović | 2020-03-14 | 2 | -0/+24 | |
| |\ | | | | | refixed parsing of constant with comment between size and value | |||||
| | * | Add regression tests for new handling of comments in constants | Marcus Comstedt | 2020-03-14 | 2 | -0/+24 | |
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| * | | Merge pull request #1754 from boqwxp/precise_locations | Miodrag Milanović | 2020-03-14 | 1 | -0/+8 | |
| |\ \ | | | | | | | Set AST node source location in more parser rules. | |||||
| | * | | verilog: add test | Eddie Hung | 2020-03-11 | 1 | -0/+8 | |
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| * | | | Added back tests for logger | Miodrag Milanovic | 2020-03-13 | 4 | -0/+24 | |
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| * | | Merge pull request #1721 from YosysHQ/dave/tribuf-unused | David Shah | 2020-03-10 | 1 | -0/+14 | |
| |\ \ | |/ |/| | deminout: Don't demote inouts with unused bits | |||||
| | * | deminout: Don't demote inouts with unused bits | David Shah | 2020-03-04 | 1 | -0/+14 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | Merge pull request #1718 from boqwxp/precise_locations | Claire Wolf | 2020-03-03 | 1 | -2/+2 | |
| |\ \ | | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. | |||||
| | * | | Change attribute search value to specify precise location instead of simple ↵ | Alberto Gonzalez | 2020-02-24 | 1 | -2/+2 | |
| | |/ | | | | | | | line number. | |||||
| * | | Merge pull request #1519 from YosysHQ/eddie/submod_po | Claire Wolf | 2020-03-03 | 1 | -0/+124 | |
| |\ \ | | | | | | | submod: several bugfixes | |||||
| | * \ | Merge branch 'master' into eddie/submod_po | Eddie Hung | 2020-02-01 | 7 | -11/+98 | |
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| | * | | | Add a quick testcase for unknown modules as inout | Eddie Hung | 2019-12-09 | 1 | -2/+24 | |
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| * | | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specify | Eddie Hung | 2020-03-02 | 2 | -19/+1 | |
| |\ \ \ \ | | | | | | | | | | | abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries | |||||
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