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* | | Allow constant function calls in for loops and generate if and caseZachary Snow2020-06-292-0/+76
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* / Use C++11 final/override keywords.whitequark2020-06-181-1/+1
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* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-1/+2
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| * abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_Eddie Hung2020-05-291-1/+2
* | Merge pull request #2080 from YosysHQ/eddie/fix_test_warningsEddie Hung2020-06-033-4/+4
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| * | tests: fix some test warningsEddie Hung2020-05-253-4/+4
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* / printattrs: Add test.Alberto Gonzalez2020-05-271-0/+14
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* xaiger: add testcaseEddie Hung2020-05-241-0/+13
* abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove itEddie Hung2020-05-141-3/+8
* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-141-2/+21
* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-141-5/+7
* Merge pull request #2028 from zachjs/masterEddie Hung2020-05-062-0/+17
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| * verilog: allow null gen-if then blockZachary Snow2020-05-062-0/+17
* | Merge pull request #2024 from YosysHQ/eddie/primitive_srcEddie Hung2020-05-051-0/+16
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| * | tests: add tests for primitives' srcEddie Hung2020-05-041-0/+16
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* / verilog: fix specify src attributeEddie Hung2020-05-041-0/+6
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* test: add test for #2014Eddie Hung2020-05-021-0/+12
* Merge pull request #1973 from YosysHQ/eddie/fix1966Eddie Hung2020-04-221-1/+3
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| * tests: use `yosys-config --datdir` instead of hard-codedEddie Hung2020-04-221-1/+3
* | Merge pull request #1950 from YosysHQ/eddie/design_importEddie Hung2020-04-222-5/+22
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| * | design: add testEddie Hung2020-04-162-5/+22
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* | Merge pull request #1976 from YosysHQ/dave/fix-sim-constClaire Wolf2020-04-221-0/+13
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| * | sim: Fix handling of constant-connected cell inputs at startupDavid Shah2020-04-211-0/+13
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* | hierarchy: Convert positional parameters to named.Marcelina Kościelnicka2020-04-211-0/+23
* | Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-2113-0/+1224
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| * | Remove '-ignore_unknown_cells' option from 'sat'Eddie Hung2020-04-201-6/+6
| * | Simplify test case scriptEddie Hung2020-04-201-30/+17
| * | Modifications of tests as per Eddie's requestdiego2020-04-2013-0/+1237
* | | abc9: add testcase reduced from #1970Eddie Hung2020-04-201-0/+19
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* | tests: add design -delete testsEddie Hung2020-04-162-0/+18
* | ast: Fix handling of identifiers in the global scopeDavid Shah2020-04-161-0/+18
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* tests: add testcases from #1876Eddie Hung2020-04-141-0/+60
* tests: add a quick plugin testEddie Hung2020-04-093-0/+22
* Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-274-0/+50
* Add test for abc9+mince issueDavid Shah2020-03-201-0/+17
* fsm_extract: Initialize celltypes with full design.Marcin Kościelnicki2020-03-191-0/+33
* Add test for `exec` command.Alberto Gonzalez2020-03-161-0/+6
* Merge pull request #1759 from zeldin/constant_with_comment_reduxMiodrag Milanović2020-03-142-0/+24
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| * Add regression tests for new handling of comments in constantsMarcus Comstedt2020-03-142-0/+24
* | Merge pull request #1754 from boqwxp/precise_locationsMiodrag Milanović2020-03-141-0/+8
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| * | verilog: add testEddie Hung2020-03-111-0/+8
* | | Added back tests for loggerMiodrag Milanovic2020-03-134-0/+24
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* | Merge pull request #1721 from YosysHQ/dave/tribuf-unusedDavid Shah2020-03-101-0/+14
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| * deminout: Don't demote inouts with unused bitsDavid Shah2020-03-041-0/+14
* | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-2/+2
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| * | Change attribute search value to specify precise location instead of simple l...Alberto Gonzalez2020-02-241-2/+2
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* | Merge pull request #1519 from YosysHQ/eddie/submod_poClaire Wolf2020-03-031-0/+124
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| * \ Merge branch 'master' into eddie/submod_poEddie Hung2020-02-017-11/+98
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| * | | Add a quick testcase for unknown modules as inoutEddie Hung2019-12-091-2/+24
* | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-022-19/+1
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