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Merge pull request #1759 from zeldin/constant_with_comment_redux
Miodrag Milanović
2020-03-14
2
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+24
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Add regression tests for new handling of comments in constants
Marcus Comstedt
2020-03-14
2
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+24
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Merge pull request #1754 from boqwxp/precise_locations
Miodrag Milanović
2020-03-14
1
-0
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+8
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verilog: add test
Eddie Hung
2020-03-11
1
-0
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+8
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Added back tests for logger
Miodrag Milanovic
2020-03-13
4
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+24
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Merge pull request #1721 from YosysHQ/dave/tribuf-unused
David Shah
2020-03-10
1
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+14
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deminout: Don't demote inouts with unused bits
David Shah
2020-03-04
1
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+14
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Merge pull request #1718 from boqwxp/precise_locations
Claire Wolf
2020-03-03
1
-2
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+2
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Change attribute search value to specify precise location instead of simple l...
Alberto Gonzalez
2020-02-24
1
-2
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+2
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Merge pull request #1519 from YosysHQ/eddie/submod_po
Claire Wolf
2020-03-03
1
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+124
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Merge branch 'master' into eddie/submod_po
Eddie Hung
2020-02-01
7
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+98
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Add a quick testcase for unknown modules as inout
Eddie Hung
2019-12-09
1
-2
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+24
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Merge pull request #1724 from YosysHQ/eddie/abc9_specify
Eddie Hung
2020-03-02
2
-19
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+1
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Cleanup tests
Eddie Hung
2020-02-27
2
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+1
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ast: fixes #1710; do not generate RTLIL for unreachable ternary
Eddie Hung
2020-02-27
1
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+30
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clean: ignore specify-s inside cells when determining whether to keep
Eddie Hung
2020-02-19
1
-1
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+20
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verilog: ignore ranges too without -specify
Eddie Hung
2020-02-13
1
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+7
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verilog: improve specify support when not in -specify mode
Eddie Hung
2020-02-13
2
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+1
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verilog: ignore '&&&' when not in -specify mode
Eddie Hung
2020-02-13
1
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+6
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specify: system timing checks to accept min:typ:max triple
Eddie Hung
2020-02-13
1
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+7
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verilog: fix $specify3 check
Eddie Hung
2020-02-13
1
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+7
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Merge pull request #1679 from thasti/delay-parsing
N. Engelhardt
2020-02-13
1
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+5
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add testcase for #1614
Stefan Biereigel
2020-02-03
1
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+5
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sv: More tests for wildcard port connections
David Shah
2020-02-02
1
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+57
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hierarchy: Correct handling of wildcard port connections with default values
David Shah
2020-02-02
1
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+11
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sv: Add tests for wildcard port connections
David Shah
2020-02-02
1
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+56
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Merge pull request #1647 from YosysHQ/dave/sprintf
David Shah
2020-02-02
1
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+12
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ast: Add support for $sformatf system function
David Shah
2020-01-19
1
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+12
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Add "help -all" and "help -celltypes" sanity test
Eddie Hung
2020-01-28
1
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+2
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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Eddie Hung
2020-01-21
1
-11
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+0
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xilinx_dsp: another typo; move xilinx specific test
Eddie Hung
2020-01-17
1
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+0
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write_xaiger: fix for (* keep *) on flop output
Eddie Hung
2020-01-21
1
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+15
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autoname: add testcase with $-prefix-ed port
Eddie Hung
2020-01-14
1
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+19
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Remove submod changes
Eddie Hung
2019-12-30
1
-102
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-20
1
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+34
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Merge pull request #1569 from YosysHQ/eddie/fix_1531
Eddie Hung
2019-12-19
1
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+34
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Add testcase
Eddie Hung
2019-12-11
1
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+34
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-19
1
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+5
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add assert option to scratchpad command
N. Engelhardt
2019-12-16
2
-14
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+5
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add test and make help message more verbose
N. Engelhardt
2019-12-12
1
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+14
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-27
1
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+31
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Add multiple driver testcase
Eddie Hung
2019-11-27
1
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+31
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-27
1
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+23
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Revert "submod to bitty rather bussy, for bussy wires used as input and output"
Eddie Hung
2019-11-27
1
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+5
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Fix wire width
Eddie Hung
2019-11-26
1
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+2
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Add testcase where \init is copied
Eddie Hung
2019-11-25
1
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+18
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Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff
Eddie Hung
2019-11-23
2
-4
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+4
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Another sloppy mistake!
Eddie Hung
2019-11-21
1
-1
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+1
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Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff
Eddie Hung
2019-11-21
2
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+2
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async2sync -> clk2fflogic
Eddie Hung
2019-11-21
1
-1
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+1
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