diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 16:07:35 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 16:07:35 -0800 |
| commit | dd317c92808a73e61e771a123fc4377d3fb78af2 (patch) | |
| tree | aa1be38bc7792f6b78b4667b6e67ce22e1b42b7e /tests/various | |
| parent | 5cd3d3db0aaa8642dad53f8fb629e3109cef5825 (diff) | |
| download | yosys-dd317c92808a73e61e771a123fc4377d3fb78af2.tar.gz yosys-dd317c92808a73e61e771a123fc4377d3fb78af2.tar.bz2 yosys-dd317c92808a73e61e771a123fc4377d3fb78af2.zip | |
Add testcase where \init is copied
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/submod.ys | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/various/submod.ys b/tests/various/submod.ys index 7c6f555ac..f50556d76 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -48,3 +48,21 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog -icells <<EOT +module top(input d, c, (* init = 1'b1 *) output reg q); +(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q)); +endmodule + +module DFF(input D, C, output Q); +parameter INIT = 1'b0; +endmodule +EOT + +hierarchy -top top + +submod +dffinit -ff DFF Q INIT +check -noinit -assert |