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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-21 16:27:40 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-21 16:27:40 -0800 |
| commit | 3d9737c1bd05235b2c32fe9daaaa9004924a6018 (patch) | |
| tree | 36c965a05ad7e1afc7baf2cf7c46922be2bd1918 /tests/various | |
| parent | cd093c00f84b44662a09d469c2b0d8ba6ecf6f6e (diff) | |
| parent | 5791c52e1b0c0e52299ee1c293a41d712d782422 (diff) | |
| download | yosys-3d9737c1bd05235b2c32fe9daaaa9004924a6018.tar.gz yosys-3d9737c1bd05235b2c32fe9daaaa9004924a6018.tar.bz2 yosys-3d9737c1bd05235b2c32fe9daaaa9004924a6018.zip | |
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/bug1462.ys | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/tests/various/bug1462.ys b/tests/various/bug1462.ys deleted file mode 100644 index 15cab5121..000000000 --- a/tests/various/bug1462.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog << EOF -module top(...); -input wire [31:0] A; -output wire [31:0] P; - -assign P = A * 32'h12300000; - -endmodule -EOF - -synth_xilinx |