iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	tests: Centralize test collection and Makefile generation	Xiretza	2020-09-21	3	-21/+5
*	flatten, techmap: don't canonicalize tpl driven bits via sigmap.	whitequark	2020-08-26	1	-0/+11
*	Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes	clairexen	2020-08-20	1	-12/+0
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\| *	techmap/shift_shiftx: Remove the "shiftx2mux" special path.	Marcelina Kościelnicka	2020-08-20	1	-12/+0
* \|	Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed	clairexen	2020-08-20	1	-0/+11
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\| * \|	peeopt.shiftmul: Add a signedness check.	Marcelina Kościelnicka	2020-08-05	1	-0/+11
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* \|	Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup	clairexen	2020-08-20	1	-50/+0
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\| * \|	Remove now-redundant dff2dffs pass.	Marcelina Kościelnicka	2020-08-07	1	-50/+0
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* /	techmap.CONSTMAP: Handle outputs before inputs.	Marcelina Kościelnicka	2020-08-05	1	-0/+15
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*	Add dffunmap pass.	Marcelina Kościelnicka	2020-07-31	1	-0/+100
*	zinit: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	1	-2/+2
*	clk2fflogic: Support all FF types.	Marcelina Kościelnicka	2020-07-24	18	-123/+123
*	techmap: Add _TECHMAP_CELLNAME_ special parameter.	Marcelina Kościelnicka	2020-07-21	1	-0/+41
*	dfflibmap: Refactor to use dfflegalize internally.	Marcelina Kościelnicka	2020-07-09	3	-0/+135
*	clkbufmap: improve input pad handling.	Marcelina Kościelnicka	2020-07-09	1	-0/+79
*	clk2fflogic: Consistently treat async control signals as negative hold.	Marcelina Kościelnicka	2020-07-09	7	-31/+31
*	dfflegalize: Add special support for const-D latches.	Marcelina Kościelnicka	2020-07-09	1	-0/+53
*	dfflegalize: Add tests.	Marcelina Kościelnicka	2020-07-01	17	-0/+2957
*	Update dff2dffe, dff2dffs, zinit to new FF types.	Marcelina Kościelnicka	2020-06-23	2	-76/+76
*	tests: zinit for new types	Eddie Hung	2020-04-14	1	-2/+96
*	dffinit: Avoid setting init parameter to zero-length value.	Marcelina Kościelnicka	2020-04-14	1	-0/+25
*	zinit: resolve one more comment by @mwkmwkmwk	Eddie Hung	2020-04-13	1	-1/+8
*	zinit: fix review comments from @mwkmwkmwk	Eddie Hung	2020-04-13	1	-4/+31
*	tests: zinit on $adff	Eddie Hung	2020-04-13	1	-19/+18
*	Add testcase for $_DFF_[NP][NP][01]_	Eddie Hung	2020-04-13	1	-0/+24
*	Merge pull request #1648 from YosysHQ/eddie/cmp2lcu	Eddie Hung	2020-04-03	1	-0/+52
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\| *	+/cmp2lcu.v to work efficiently for fully/partially constant inputs	Eddie Hung	2020-04-03	1	-3/+31
\| *	Refactor +/cmp2lcu.v into recursive techmap	Eddie Hung	2020-04-03	1	-1/+1
\| *	techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu	Eddie Hung	2020-04-03	1	-0/+24
* \|	iopadmap: Fix z assignment to inout port	Marcin Kościelnicki	2020-04-02	1	-1/+9
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*	techmap: Fix cell names with _TECHMAP_REPLACE_.*	Marcin Kościelnicki	2020-03-23	1	-0/+18
*	iopadmap: Look harder for already-present buffers. (#1731)	Marcelina Kościelnicka	2020-03-02	1	-2/+21
*	Fine tune #1699 tests	Eddie Hung	2020-02-13	1	-14/+14
*	iopadmap: move \init attributes from outpad output to its input	Eddie Hung	2020-02-13	1	-0/+37
*	shiftx2mux: fix select out of bounds	Eddie Hung	2020-02-05	2	-1/+12
*	Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux	Eddie Hung	2020-02-05	1	-0/+29
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\| *	Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor	Eddie Hung	2020-01-15	1	-0/+13
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\| * \|	abc9: respect (* keep *) on cells	Eddie Hung	2020-01-13	1	-0/+15
\| * \|	write_xaiger: add support and test for (* keep *) on wires	Eddie Hung	2020-01-13	1	-0/+13
* \| \|	Move from +/shiftx2mux.v into +/techmap.v; cleanup	Eddie Hung	2020-01-21	1	-4/+4
* \| \|	New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC	Eddie Hung	2020-01-21	1	-0/+110
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* \|	abc9: aAdd test to check $_NOT_s are absorbed	Eddie Hung	2020-01-15	1	-0/+12
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*	Add abc9 sanity test	Eddie Hung	2020-01-09	1	-0/+40
*	iopadmap: Emit tristate buffers with const OE for some edge cases.	Marcin Kościelnicki	2019-12-25	1	-0/+23
*	iopadmap: Refactor and fix tristate buffer mapping. (#1527)	Marcin Kościelnicki	2019-12-04	1	-0/+99
*	clkbufmap: Add support for inverters in clock path.	Marcin Kościelnicki	2019-11-25	1	-5/+16
*	Merge pull request #1422 from YosysHQ/eddie/aigmap_select	Clifford Wolf	2019-10-03	1	-0/+10
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\| *	Add quick test	Eddie Hung	2019-09-30	1	-0/+10
* \|	Extend test with renaming cells with prefix too	Eddie Hung	2019-10-02	1	-0/+2
* \|	Add test	Eddie Hung	2019-09-30	1	-0/+16
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