iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	verific: Use new value change logic also for $stable of wide signals.	Jannis Harder	2022-05-11	2	-2/+43
*	Merge pull request #3305 from jix/sva_value_change_logic	Jannis Harder	2022-05-09	7	-1/+96
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\| *	verific: Improve logic generated for SVA value change expressions	Jannis Harder	2022-05-09	7	-1/+96
* \|	Merge pull request #3297 from jix/sva_nested_clk_else	Jannis Harder	2022-05-09	1	-0/+11
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\| *	verific: Fix conditions of SVAs with explicit clocks within procedures	Jannis Harder	2022-05-03	1	-0/+11
* \|	Fix running sva tests	Miodrag Milanovic	2022-05-09	1	-4/+3
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*	Fix "verific -extnets" for more complex situations	Clifford Wolf	2019-03-26	1	-0/+22
*	Squelch a little more trailing whitespace	Larry Doolittle	2018-12-29	1	-1/+1
*	Major redesign of Verific SVA importer	Clifford Wolf	2018-02-27	1	-1/+1
*	Add support for SVA throughout via Verific	Clifford Wolf	2018-02-21	1	-1/+1
*	Add support for SVA sequence concatenation ranges via verific	Clifford Wolf	2018-02-18	2	-0/+20
*	Add support for SVA until statements via Verific	Clifford Wolf	2018-02-18	1	-0/+19
*	Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF	Clifford Wolf	2018-02-15	1	-0/+34
*	Remove PSL example from tests/sva/	Clifford Wolf	2017-10-20	2	-35/+1
*	Add simple VHDL+PSL example	Clifford Wolf	2017-07-28	4	-17/+64
*	Improve Verific SVA importer	Clifford Wolf	2017-07-27	1	-7/+8
*	Add counter.sv SVA test	Clifford Wolf	2017-07-27	1	-0/+29
*	Improve SVA tests, add Makefile and scripts	Clifford Wolf	2017-07-27	11	-9/+110
*	Add more SVA test cases for future Verific work	Clifford Wolf	2017-07-22	5	-1/+74
*	Add some simple SVA test cases for future Verific work	Clifford Wolf	2017-07-22	4	-0/+45