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| author | Clifford Wolf <clifford@clifford.at> | 2018-02-21 13:09:47 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-21 13:09:47 +0100 |
| commit | 6d12c83d362c709f72e64eea2121b2cffc12ee8d (patch) | |
| tree | db9f4bbd23313bb58468e24d191e38713cc73e77 /tests/sva | |
| parent | 17583b6a2175bf509d6a233e5684a183af54f48c (diff) | |
| download | yosys-6d12c83d362c709f72e64eea2121b2cffc12ee8d.tar.gz yosys-6d12c83d362c709f72e64eea2121b2cffc12ee8d.tar.bz2 yosys-6d12c83d362c709f72e64eea2121b2cffc12ee8d.zip | |
Add support for SVA throughout via Verific
Diffstat (limited to 'tests/sva')
| -rw-r--r-- | tests/sva/sva_throughout.sv (renamed from tests/sva/sva_until.sv) | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/sva/sva_until.sv b/tests/sva/sva_throughout.sv index a721e44b5..7e036a066 100644 --- a/tests/sva/sva_until.sv +++ b/tests/sva/sva_throughout.sv @@ -5,7 +5,7 @@ module top ( default clocking @(posedge clk); endclocking assert property ( - a |=> b until_with (c ##1 d) + a |=> b throughout (c ##1 d) ); `ifndef FAIL |