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| author | Clifford Wolf <clifford@clifford.at> | 2018-02-18 14:57:52 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-18 14:57:52 +0100 |
| commit | 9d963cd29c499530bc4bcc66f298a6e56142c509 (patch) | |
| tree | ee2f60c2653da3f38141c3a75872db225154727e /tests/sva | |
| parent | 5fa2aa27417447e62cee6edfbf6c1fb07d7b17b0 (diff) | |
| download | yosys-9d963cd29c499530bc4bcc66f298a6e56142c509.tar.gz yosys-9d963cd29c499530bc4bcc66f298a6e56142c509.tar.bz2 yosys-9d963cd29c499530bc4bcc66f298a6e56142c509.zip | |
Add support for SVA until statements via Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'tests/sva')
| -rw-r--r-- | tests/sva/sva_until.sv | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/tests/sva/sva_until.sv b/tests/sva/sva_until.sv new file mode 100644 index 000000000..a721e44b5 --- /dev/null +++ b/tests/sva/sva_until.sv @@ -0,0 +1,19 @@ +module top ( + input clk, + input a, b, c, d +); + default clocking @(posedge clk); endclocking + + assert property ( + a |=> b until_with (c ##1 d) + ); + +`ifndef FAIL + assume property ( + a |=> b && c + ); + assume property ( + b && c |=> b && d + ); +`endif +endmodule |