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* FfData: some refactoring.Marcelina Kościelnicka2021-10-071-2/+3
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-0/+7
* Gowin: deal with active-low tristate (#2971)Pepijn de Vos2021-08-201-1/+2
* test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.Marcelina Kościelnicka2021-08-112-78/+156
* Add v2 memory cells.Marcelina Kościelnicka2021-08-112-25/+25
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-0/+24
* Fix files with CRLF line endingsClaire Xenia Wolf2021-06-093-73/+73
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-254-17/+14
* intel_alm: Fix illegal carry chainsgatecat2021-05-152-4/+4
* intel_alm: Add global buffer insertiongatecat2021-05-1513-41/+41
* intel_alm: Add IO buffer insertiongatecat2021-05-1513-39/+39
* Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-201-1/+1
* quicklogic: ABC9 synthesisLofty2021-04-176-17/+17
* quicklogic: Add .gitignore file for test outputs.Marcelina Kościelnicka2021-03-231-0/+4
* quicklogic: PolarPro 3 supportLofty2021-03-1810-0/+262
* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-3/+3
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-9/+9
* machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ...William D. Jones2021-02-231-1/+1
* machxo2: Update tribuf test to reflect active-low OE.William D. Jones2021-02-231-1/+2
* machxo2: Add believed-to-be-correct tribuf test.William D. Jones2021-02-231-0/+9
* machxo2: Add passing fsm, mux, and shifter tests.William D. Jones2021-02-233-0/+65
* machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives.William D. Jones2021-02-233-3/+11
* machxo2: Add dffe test.William D. Jones2021-02-231-0/+9
* machxo2: Add dff.ys test, fix another cells_map.v typo.William D. Jones2021-02-231-0/+10
* machxo2: Add test/arch/machxo2 directory (test does not pass).William D. Jones2021-02-233-0/+14
* xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-272-1/+48
* nexus: DSP inference supportDavid Shah2020-11-201-12/+34
* Update nexus arch tests to new harnessXiretza2020-10-291-19/+3
* xilinx: Fix attributes_test.ysMarcelina Kościelnicka2020-10-241-4/+2
* memory_dff: Fix needlessly duplicating enable bits.Marcelina Kościelnicka2020-10-221-0/+24
* Merge pull request #2397 from daveshah1/nexusMiodrag Milanović2020-10-1915-0/+298
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| * synth_nexus: Initial implementationDavid Shah2020-10-1515-0/+298
* | Merge pull request #2380 from Xiretza/parallel-testsclairexen2020-10-017-133/+21
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| * tests: Centralize test collection and Makefile generationXiretza2020-09-217-133/+21
* | xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)Eddie Hung2020-09-231-0/+37
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* intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-262-6/+44
* techmap/shift_shiftx: Remove the "shiftx2mux" special path.Marcelina Kościelnicka2020-08-201-2/+3
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-077-31/+28
* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-311-2/+1
* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-301-1/+1
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-9/+7
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-271-0/+6
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-6/+6
* satgen: Add support for dffe, sdff, sdffe, sdffce cells.Marcelina Kościelnicka2020-07-241-2/+0
* intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-231-6/+4
* Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogicMiodrag Milanović2020-07-161-12/+14
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| * anlogic: Use dfflegalize.Marcelina Kościelnicka2020-07-141-12/+14
* | Revert "intel_alm: direct M10K instantiation"Lofty2020-07-131-6/+0
* | xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-0/+41
* | gowin: Use dfflegalize.Marcelina Kościelnicka2020-07-062-13/+8
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