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| author | David Shah <dave@ds0.me> | 2020-11-20 08:26:58 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2020-11-20 08:45:55 +0000 |
| commit | 9f241c9a42d9380164a9df8f16cf9dffb10bc8ad (patch) | |
| tree | 29d45faf9380a5cd5144d2334cca41febc6ebe4d /tests/arch | |
| parent | 5b35d953f749beafeceecc67862419221e91fe84 (diff) | |
| download | yosys-9f241c9a42d9380164a9df8f16cf9dffb10bc8ad.tar.gz yosys-9f241c9a42d9380164a9df8f16cf9dffb10bc8ad.tar.bz2 yosys-9f241c9a42d9380164a9df8f16cf9dffb10bc8ad.zip | |
nexus: DSP inference support
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/nexus/mul.ys | 46 |
1 files changed, 34 insertions, 12 deletions
diff --git a/tests/arch/nexus/mul.ys b/tests/arch/nexus/mul.ys index 27ea3e04e..65a2fd8c3 100644 --- a/tests/arch/nexus/mul.ys +++ b/tests/arch/nexus/mul.ys @@ -1,4 +1,5 @@ read_verilog ../common/mul.v +chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 hierarchy -top top proc @@ -7,22 +8,43 @@ design -save read equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 7 t:CCU2 -select -assert-max 5 t:WIDEFN9 -select -assert-max 62 t:LUT4 +select -assert-count 1 t:MULT9X9 -select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D +select -assert-none t:IB t:OB t:VLO t:VHI t:MULT9X9 %% t:* %D -design -load read -equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9 -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_nexus +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X18 +select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X18 %% t:* %D + + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_nexus cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X36 +select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X36 %% t:* %D -stat -select -assert-count 7 t:CCU2 -select -assert-max 12 t:WIDEFN9 -select -assert-max 58 t:LUT4 +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_nexus +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT36X36 -select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D +select -assert-none t:IB t:OB t:VLO t:VHI t:MULT36X36 %% t:* %D |