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| author | William D. Jones <thor0505@comcast.net> | 2020-11-17 14:35:17 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | 84937e9689c6fddfc613356f9a629d7628939668 (patch) | |
| tree | 11208b7397e9870d82613293425b3beb7ddc39ae /tests/arch | |
| parent | 044393b990316d997df3a5cc57e9d065c3a5e9d8 (diff) | |
| download | yosys-84937e9689c6fddfc613356f9a629d7628939668.tar.gz yosys-84937e9689c6fddfc613356f9a629d7628939668.tar.bz2 yosys-84937e9689c6fddfc613356f9a629d7628939668.zip | |
machxo2: Add dff.ys test, fix another cells_map.v typo.
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/machxo2/dffs.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/arch/machxo2/dffs.ys b/tests/arch/machxo2/dffs.ys new file mode 100644 index 000000000..3e9f87fec --- /dev/null +++ b/tests/arch/machxo2/dffs.ys @@ -0,0 +1,10 @@ +read_verilog ../common/dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:FACADE_FF +select -assert-none t:FACADE_FF %% t:* %D |