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| author | Marcin Kościelnicki <mwk@0x04.net> | 2020-02-03 18:37:28 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-02-07 09:03:22 +0100 |
| commit | 89adef352fde57fa599d66fe404c3c2b9e607a7f (patch) | |
| tree | 57dc27856458c388187570d43178f43f3503bb46 /tests/arch/xilinx | |
| parent | d48950d92d748cc24ecfefc5beab19ea899982df (diff) | |
| download | yosys-89adef352fde57fa599d66fe404c3c2b9e607a7f.tar.gz yosys-89adef352fde57fa599d66fe404c3c2b9e607a7f.tar.bz2 yosys-89adef352fde57fa599d66fe404c3c2b9e607a7f.zip | |
xilinx: Add support for LUT RAM on LUT4-based devices.
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.
Fixes #1549
Diffstat (limited to 'tests/arch/xilinx')
| -rw-r--r-- | tests/arch/xilinx/lutram.ys | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index 3f127a77e..cc7354501 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -135,3 +135,23 @@ select -assert-count 1 t:BUFG select -assert-count 6 t:FDRE select -assert-count 2 t:RAM64M select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 4 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -family xc3s -noiopad +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM16X1D +select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D |