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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 07:18:21 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 08:43:33 -0700 |
| commit | 8dd93e389eecebbe005886452cd60edefdbdc21a (patch) | |
| tree | e7c40060c6c34ce9e46de2572146098d537aa560 /tests/arch/xilinx | |
| parent | 1ebf7155a7d96a529432d93979fb553f12b9d641 (diff) | |
| download | yosys-8dd93e389eecebbe005886452cd60edefdbdc21a.tar.gz yosys-8dd93e389eecebbe005886452cd60edefdbdc21a.tar.bz2 yosys-8dd93e389eecebbe005886452cd60edefdbdc21a.zip | |
tests: add testcase for abc9 -dff preserving flop names
Diffstat (limited to 'tests/arch/xilinx')
| -rw-r--r-- | tests/arch/xilinx/abc9_dff.ys | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys index fd343969b..c549e1fdc 100644 --- a/tests/arch/xilinx/abc9_dff.ys +++ b/tests/arch/xilinx/abc9_dff.ys @@ -82,4 +82,38 @@ select -assert-count 1 t:FDPE select -assert-count 2 t:INV select -assert-count 0 t:FD* t:INV %% t:* %D + +design -reset +read_verilog <<EOT +module top(input clk, input d, output q); +reg r; +always @(posedge clk) begin +r <= d; +end +assign q = ~r; +endmodule +EOT +proc +equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf +design -load postopt +select -assert-count 1 t:FDRE %co w:r %i + + +design -reset +read_verilog <<EOT +module top(input clk, input a, b, output reg q1, output q2); +reg r; +always @(posedge clk) begin + q1 <= a | b; + r <= ~(~a & ~b); +end +assign q2 = r; +endmodule +EOT +proc +equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf +design -load postopt +select -assert-count 1 t:FDRE %co %a w:r %i + + logger -expect-no-warnings |