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* Fix for sync_ram_sdp not being final moduleKrystalDelusion2023-02-211-1/+1
* Reenable existing equiv_opt testsJannis Harder2022-10-071-2/+2
* intel_alm: M10K write-enable is negative-trueLofty2022-03-091-1/+2
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-251-6/+4
* intel_alm: Fix illegal carry chainsgatecat2021-05-152-4/+4
* intel_alm: Add global buffer insertiongatecat2021-05-1513-41/+41
* intel_alm: Add IO buffer insertiongatecat2021-05-1513-39/+39
* tests: Centralize test collection and Makefile generationXiretza2020-09-211-19/+3
* intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-261-3/+40
* techmap/shift_shiftx: Remove the "shiftx2mux" special path.Marcelina Kościelnicka2020-08-201-2/+3
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-072-11/+11
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-271-0/+6
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-6/+6
* intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-231-6/+4
* Revert "intel_alm: direct M10K instantiation"Lofty2020-07-131-6/+0
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-051-0/+6
* intel_alm: add Cyclone 10 GX testsDan Ravensloft2020-07-0511-2/+236
* intel_alm: DSP inferenceDan Ravensloft2020-07-051-0/+23
* synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-041-1/+1
* Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-041-1/+2
* tests: update fsm.ys resource countEddie Hung2020-07-041-4/+4
* intel_alm: fix DFFE matchingDan Ravensloft2020-06-112-4/+4
* Add missing .gitignore fileClaire Wolf2020-06-041-0/+2
* intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-071-0/+20
* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+12
* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1510-0/+208