iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	ice40: Use `memory_libmap` pass.	Marcelina Kościelnicka	2022-05-18	1	-56/+0
*	test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.	Marcelina Kościelnicka	2021-08-11	1	-27/+54
*	Add v2 memory cells.	Marcelina Kościelnicka	2021-08-11	1	-8/+8
*	opt_lut: Allow more than one -dlogic per cell type.	Marcelina Kościelnicka	2021-07-29	1	-0/+24
*	tests: Centralize test collection and Makefile generation	Xiretza	2020-09-21	1	-19/+3
*	synth_ice40: Use opt_dff.	Marcelina Kościelnicka	2020-07-30	1	-1/+1
*	allow range for mux test	Miodrag Milanovic	2020-06-01	1	-1/+2
*	test: ice40_dsp test to read +/ice40/cells_sim.v for default params	Eddie Hung	2020-04-22	1	-0/+1
*	tests: remove write_ilang	Eddie Hung	2020-04-20	1	-1/+0
*	Merge pull request #1603 from whitequark/ice40-ram_style	whitequark	2020-04-10	2	-15/+168
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\| *	ice40: do not map FFRAM if explicitly requested otherwise.	whitequark	2020-04-03	1	-8/+28
\| *	ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.	whitequark	2020-02-06	1	-0/+16
\| *	ice40: match memory inference attribute values case insensitive.	whitequark	2020-02-06	1	-0/+6
\| *	ice40: add support for both 1364.1 and LSE RAM/ROM attributes.	whitequark	2020-02-06	1	-0/+126
\| *	ice40: remove impossible test.	whitequark	2020-02-06	1	-15/+0
* \|	Change attribute search value to specify precise location instead of simple l...	Alberto Gonzalez	2020-02-24	1	-2/+2
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*	Import tests from #1628	Eddie Hung	2020-01-27	2	-0/+102
*	ice40: reduce ABC9 internal fanout warnings with a param for CI->I3	Eddie Hung	2020-01-24	1	-23/+4
*	Add #1644 testcase	Eddie Hung	2020-01-17	2	-0/+2
*	ice40_dsp: add test	Eddie Hung	2020-01-17	1	-0/+11
*	Add #1626 testcase	Eddie Hung	2020-01-12	1	-0/+217
*	Revert insertion of 'reg', leave note behind	Eddie Hung	2020-01-01	1	-1/+2
*	Fix warnings	Eddie Hung	2019-12-31	2	-2/+2
*	Call equiv_opt with -multiclock and -assert	Eddie Hung	2019-12-31	1	-1/+1
*	Add #1598 testcase	Eddie Hung	2019-12-27	1	-0/+16
*	Rename memory tests to lutram, add more xilinx tests	Eddie Hung	2019-12-12	1	-3/+3
*	unmap $__ICE40_CARRY_WRAPPER in test	Eddie Hung	2019-12-09	1	-1/+21
*	ice40_wrapcarry to really preserve attributes via -unwrap option	Eddie Hung	2019-12-09	1	-3/+5
*	Drop keep=0 attributes on SB_CARRY	Eddie Hung	2019-12-06	1	-2/+2
*	Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER	Eddie Hung	2019-12-05	1	-0/+30
*	Check SB_CARRY name also preserved	Eddie Hung	2019-12-03	1	-0/+1
*	Add testcase	Eddie Hung	2019-12-03	1	-0/+60
*	Fixed tests	Miodrag Milanovic	2019-11-11	1	-5/+8
*	Common memory test now shared	Miodrag Milanovic	2019-10-18	2	-22/+1
*	Remove not needed tests	Miodrag Milanovic	2019-10-18	4	-52/+0
*	Share common tests	Miodrag Milanovic	2019-10-18	22	-494/+127
*	Fix path to yosys	Miodrag Milanovic	2019-10-18	1	-1/+1
*	Moved all tests in arch sub directory	Miodrag Milanovic	2019-10-18	38	-0/+861