index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
tests
/
arch
/
ecp5
Commit message (
Expand
)
Author
Age
Files
Lines
*
tests: remove write_ilang
Eddie Hung
2020-04-20
1
-2
/
+0
*
Merge pull request #1603 from whitequark/ice40-ram_style
whitequark
2020-04-10
1
-0
/
+330
|
\
|
*
ecp5: do not map FFRAM if explicitly requested otherwise.
whitequark
2020-04-03
1
-16
/
+62
|
*
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
whitequark
2020-02-06
1
-0
/
+284
*
|
Update bug1630.ys to use -lut 4 instead of lut file
Eddie Hung
2020-02-27
1
-1
/
+1
|
/
*
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
Eddie Hung
2020-02-05
1
-0
/
+32
|
\
|
*
Add opt_lut_ins pass. (#1673)
Marcelina Kościelnicka
2020-02-03
1
-0
/
+32
*
|
Update tests with reduced area
Eddie Hung
2020-01-21
1
-3
/
+3
|
/
*
Add #1630 testcase
Eddie Hung
2020-01-13
2
-0
/
+2
*
Add testcase from #1459
Eddie Hung
2020-01-06
1
-0
/
+25
*
Do not do call equiv_opt when no sim model exists
Eddie Hung
2019-12-31
2
-4
/
+4
*
Call equiv_opt with -multiclock and -assert
Eddie Hung
2019-12-31
1
-1
/
+1
*
Merge pull request #1599 from YosysHQ/eddie/retry_1588
Eddie Hung
2019-12-30
1
-0
/
+16
|
\
|
*
Add #1598 testcase
Eddie Hung
2019-12-27
1
-0
/
+16
*
|
Update resource count
Eddie Hung
2019-12-28
1
-3
/
+3
|
/
*
Rename memory tests to lutram, add more xilinx tests
Eddie Hung
2019-12-12
1
-3
/
+3
*
Fixed tests
Miodrag Milanovic
2019-11-11
1
-4
/
+9
*
Common memory test now shared
Miodrag Milanovic
2019-10-18
2
-22
/
+1
*
Share common tests
Miodrag Milanovic
2019-10-18
22
-302
/
+11
*
Fix path to yosys
Miodrag Milanovic
2019-10-18
1
-1
/
+1
*
Moved all tests in arch sub directory
Miodrag Milanovic
2019-10-18
32
-0
/
+668
