| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | memory_dff: Remove now-useless write port handling. | Marcelina Kościelnicka | 2021-03-08 | 1 | -6/+7 |
| | | |||||
| * | Fix syntax error in adff2dff.v | Marcelina Kościelnicka | 2021-02-24 | 1 | -1/+1 |
| | | | | | Fixes #2600. | ||||
| * | machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ↵ | William D. Jones | 2021-02-23 | 1 | -11/+5 |
| | | | | | values. | ||||
| * | machxo2: Add experimental status to help. | William D. Jones | 2021-02-23 | 1 | -1/+1 |
| | | |||||
| * | machxo2: Add DCCA and DCMA blackbox primitives. | William D. Jones | 2021-02-23 | 1 | -0/+17 |
| | | |||||
| * | machxo2: Fix reversed interpretation of REG_SD config bits. | William D. Jones | 2021-02-23 | 1 | -2/+2 |
| | | |||||
| * | machxo2: Tristate is active-low. | William D. Jones | 2021-02-23 | 2 | -5/+5 |
| | | |||||
| * | machxo2: Fix typos in FACADE_FF sim model. | William D. Jones | 2021-02-23 | 1 | -5/+4 |
| | | |||||
| * | machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph. | William D. Jones | 2021-02-23 | 2 | -6/+6 |
| | | |||||
| * | machxo2: Improve help_mode output in synth_machxo2. | William D. Jones | 2021-02-23 | 1 | -5/+5 |
| | | |||||
| * | machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires ↵ | William D. Jones | 2021-02-23 | 2 | -1/+17 |
| | | | | | to IO cells. | ||||
| * | machxo2: Add missing OSCH oscillator primitive. | William D. Jones | 2021-02-23 | 1 | -0/+10 |
| | | |||||
| * | machxo2: Add -noiopad option to synth_machxo2. | William D. Jones | 2021-02-23 | 1 | -2/+11 |
| | | |||||
| * | machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE. | William D. Jones | 2021-02-23 | 1 | -1/+1 |
| | | |||||
| * | machxo2: Fix cells_sim typo where OFX1 was multiply-driven. | William D. Jones | 2021-02-23 | 1 | -1/+1 |
| | | |||||
| * | machxo2: synth_machxo2 now maps ports to FACADE_IO. | William D. Jones | 2021-02-23 | 2 | -0/+12 |
| | | |||||
| * | machxo2: Add initial value for Q in FACADE_FF. | William D. Jones | 2021-02-23 | 1 | -0/+2 |
| | | |||||
| * | machxo2: Add FACADE_IO simulation model. More comments on models. | William D. Jones | 2021-02-23 | 1 | -0/+25 |
| | | |||||
| * | machxo2: Add FACADE_SLICE simulation model. | William D. Jones | 2021-02-23 | 1 | -0/+83 |
| | | |||||
| * | machxo2: Improve FACADE_FF simulation model. | William D. Jones | 2021-02-23 | 1 | -12/+20 |
| | | |||||
| * | machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice. | William D. Jones | 2021-02-23 | 2 | -4/+4 |
| | | |||||
| * | machxo2: Add dff.ys test, fix another cells_map.v typo. | William D. Jones | 2021-02-23 | 1 | -1/+1 |
| | | |||||
| * | machxo2: Fix more oversights in machxo2 models. logic.ys test passes. | William D. Jones | 2021-02-23 | 2 | -2/+6 |
| | | |||||
| * | machxo2: Fix typos. test/arch/run-test.sh passes. | William D. Jones | 2021-02-23 | 2 | -2/+2 |
| | | |||||
| * | machxo2: Create basic techlibs and synth_machxo2 pass. | William D. Jones | 2021-02-23 | 4 | -0/+320 |
| | | |||||
| * | Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct | gatecat | 2021-02-12 | 1 | -0/+115 |
| |\ | | | | | nexus: Add MULTADDSUB9X9WIDE sim model | ||||
| | * | nexus: Add MULTADDSUB9X9WIDE sim model | David Shah | 2020-12-08 | 1 | -0/+115 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | verilog: significant block scoping improvements | Zachary Snow | 2021-01-31 | 5 | -81/+89 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493 | ||||
| * | | xilinx_dffopt: Don't crash on missing IS_*_INVERTED. | Marcelina Kościelnicka | 2021-01-27 | 1 | -3/+3 |
| | | | | | | | | | | | | | | | | | The presence of IS_*_INVERTED on FD* cells follows Vivado, which apparently has been decided by a dice roll. Just assume false if the parameter doesn't exist. Fixes #2559. | ||||
| * | | xilinx: Add FDRSE_1, FDCPE_1. | Marcelina Kościelnicka | 2021-01-27 | 1 | -0/+80 |
| | | | |||||
| * | | Fix some trivial typos. | Tom Verbeure | 2021-01-03 | 1 | -5/+5 |
| | | | |||||
| * | | Merge pull request #2480 from YosysHQ/dave/nexus-lram | whitequark | 2021-01-01 | 5 | -1/+227 |
| |\| | | | | | nexus: Add LRAM inference | ||||
| | * | nexus: Add LRAM inference | David Shah | 2020-12-07 | 5 | -1/+227 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | xilinx: Add some missing blackbox cells. | Marcelina Kościelnicka | 2020-12-21 | 3 | -798/+6276 |
| | | | |||||
| * | | xilinx: Regenerate cells_xtra.v using Vivado 2020.2 | Marcelina Kościelnicka | 2020-12-21 | 2 | -42/+49 |
| | | | |||||
| * | | xilinx: Add FDDRCPE and FDDRRSE blackbox cells. | Marcelina Kościelnicka | 2020-12-17 | 2 | -0/+33 |
| |/ | | | | | These are necessary primitives for proper DDR support on Virtex 2 and Spartan 3. | ||||
| * | nexus: More efficient CO mapping | David Shah | 2020-12-02 | 1 | -2/+2 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | add -noalu and -json option for apicula | Pepijn de Vos | 2020-11-30 | 1 | -3/+32 |
| | | |||||
| * | nexus: DSP inference support | David Shah | 2020-11-20 | 3 | -1/+117 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Merge pull request #2441 from YosysHQ/dave/nexus_dsp_sim | Miodrag Milanović | 2020-11-18 | 3 | -250/+573 |
| |\ | | | | | nexus: Add DSP simulation model | ||||
| | * | nexus: Add DSP simulation model | David Shah | 2020-11-18 | 3 | -250/+573 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | Fix duplicated parameter name typo | Miodrag Milanovic | 2020-11-18 | 1 | -1/+1 |
| | | | |||||
| * | | synth_gowin: Add rPLL blackbox | Konrad Beckmann | 2020-11-11 | 1 | -0/+45 |
| |/ | |||||
| * | nexus: Add make_transp to BRAMs | David Shah | 2020-10-22 | 1 | -0/+3 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Merge pull request #2405 from byuccl/fix_xilinx_cells | clairexen | 2020-10-20 | 1 | -2/+2 |
| |\ | | | | | xilinx/cells_sim.v: Move signal declaration to before first use | ||||
| | * | Move signal declarations to before first use | Jeff Goeders | 2020-10-19 | 1 | -2/+2 |
| | | | | | | | | | Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com> | ||||
| * | | synth_nexus: Initial implementation | David Shah | 2020-10-15 | 14 | -0/+12229 |
| |/ | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) | Eddie Hung | 2020-09-23 | 2 | -17/+65 |
| | | | | | | | | | | | | * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled | ||||
| * | intel_alm: better map wide but shallow multiplies | Dan Ravensloft | 2020-08-28 | 1 | -2/+6 |
| | | |||||
| * | intel_alm: Add multiply signedness to cells | Dan Ravensloft | 2020-08-26 | 5 | -10/+103 |
| | | | | | | | Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells. | ||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |