iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	xilinx: Add xilinx_dffopt pass (#1557)	Marcin Kościelnicki	2019-12-18	6	-22/+389
*	xilinx: Improve flip-flop handling.	Marcin Kościelnicki	2019-12-18	4	-38/+228
*	Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram	Eddie Hung	2019-12-16	3	-12/+301
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\| *	Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xil...	Eddie Hung	2019-12-16	1	-2/+8
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\| \| *	Populate DID/DOD even if unused	Eddie Hung	2019-12-16	1	-2/+8
\| * \|	Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q	Eddie Hung	2019-12-16	2	-6/+6
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\| *	Disable RAM16X1D match rule; carry-over from LUT4 arches	Eddie Hung	2019-12-13	1	-6/+9
\| *	RAM64M8 to also have [5:0] for address	Eddie Hung	2019-12-13	1	-8/+8
\| *	Add RAM32X6SDP and RAM64X3SDP modes	Eddie Hung	2019-12-12	2	-8/+120
\| *	Fix RAM64M model to have 6 bit address bus	Eddie Hung	2019-12-12	1	-4/+4
\| *	Add memory rules for RAM16X1D, RAM32M, RAM64M	Eddie Hung	2019-12-12	2	-0/+168
* \|	Add unconditional match blocks for force RAM	Eddie Hung	2019-12-16	1	-4/+36
* \|	Update xc7/xcu bram rules	Eddie Hung	2019-12-16	1	-8/+4
* \|	Removing fixed attribute value to !ramstyle rules	Diego H	2019-12-15	1	-4/+4
* \|	Merging attribute rules into a single match block; Adding tests	Diego H	2019-12-15	1	-18/+12
* \|	Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific	Diego H	2019-12-13	1	-0/+19
* \|	Merge pull request #1533 from dh73/bram_xilinx	Eddie Hung	2019-12-13	1	-6/+9
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\| *	Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.	Diego H	2019-12-12	1	-5/+5
\| *	Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1	Diego H	2019-12-12	1	-2/+2
\| *	Merge https://github.com/YosysHQ/yosys into bram_xilinx	Diego H	2019-12-12	20	-775/+1170
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\| * \|	Adjusting Vivado's BRAM min bits threshold for RAMB18E1	Diego H	2019-11-27	1	-2/+5
* \| \|	abc9_map.v: fix Xilinx LUTRAM	Eddie Hung	2019-12-12	1	-6/+6
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* \|	Fix bitwidth mismatch; suppresses iverilog warning	Eddie Hung	2019-12-11	1	-4/+4
* \|	Merge pull request #1564 from ZirconiumX/intel_housekeeping	David Shah	2019-12-11	8	-6/+6
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\| * \|	synth_intel: a10gx -> arria10gx	Dan Ravensloft	2019-12-10	5	-4/+4
\| * \|	synth_intel: cyclone10 -> cyclone10lp	Dan Ravensloft	2019-12-10	5	-4/+4
* \| \|	Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr	Eddie Hung	2019-12-09	4	-20/+22
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\| * \|	ice40_opt to restore attributes/name when unwrapping	Eddie Hung	2019-12-09	1	-0/+15
\| * \|	Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4	Eddie Hung	2019-12-09	1	-1/+1
\| * \|	ice40_wrapcarry to really preserve attributes via -unwrap option	Eddie Hung	2019-12-09	2	-19/+1
\| * \|	$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve	Eddie Hung	2019-12-03	1	-1/+1
\| * \|	ice40_opt to ignore (* keep *) -ed cells	Eddie Hung	2019-12-03	1	-0/+5
* \| \|	xilinx: Add tristate buffer mapping. (#1528)	Marcin Kościelnicki	2019-12-04	2	-9/+16
* \| \|	xilinx: Add models for LUTRAM cells. (#1537)	Marcin Kościelnicki	2019-12-04	3	-624/+831
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* \|	Merge pull request #1524 from pepijndevos/gowindffinit	Clifford Wolf	2019-12-03	2	-112/+270
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\| * \|	Use -match-init to not synth contradicting init values	Pepijn de Vos	2019-12-03	1	-1/+1
\| * \|	attempt to fix formatting	Pepijn de Vos	2019-11-25	1	-154/+154
\| * \|	gowin: add and test dff init values	Pepijn de Vos	2019-11-25	2	-41/+199
* \| \|	xilinx: Add missing blackbox cell for BUFPLL.	Marcin Kościelnicki	2019-11-29	2	-0/+21
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* \|	xilinx: Add simulation models for IOBUF and OBUFT.	Marcin Kościelnicki	2019-11-26	3	-25/+30
* \|	clkbufmap: Add support for inverters in clock path.	Marcin Kościelnicki	2019-11-25	1	-1/+5
* \|	xilinx: Use INV instead of LUT1 when applicable	Marcin Kościelnicki	2019-11-25	1	-2/+6
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*	coolrunner2: remove spurious log_pop() call, fixes #1463	Martin Pietryka	2019-11-23	1	-2/+0
*	gowin: Add missing .gitignore entries	Marcin Kościelnicki	2019-11-22	1	-0/+2
*	Merge pull request #1449 from pepijndevos/gowin	Clifford Wolf	2019-11-19	8	-43/+547
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\| *	Remove dff init altogether	Pepijn de Vos	2019-11-19	2	-3/+3
\| *	add help for nowidelut and abc9 options	Pepijn de Vos	2019-11-18	1	-1/+7
\| *	Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin	Pepijn de Vos	2019-11-16	4	-15/+439
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\| * \|	fix fsm test with proper clock enable polarity	Pepijn de Vos	2019-11-11	1	-4/+4
\| * \|	Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin	Pepijn de Vos	2019-11-11	22	-22988/+30572
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