synth_intel: cyclone10 -> cyclone10lp

5 files changed, 4 insertions, 4 deletions

diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc
index 4e8f423c8..92a83b5af 100644
--- a/techlibs/intel/Makefile.inc
+++ b/techlibs/intel/Makefile.inc
@@ -7,7 +7,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.
 $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
 
 # Add the cell models and mappings for the VQM backend
-families := max10 a10gx cyclonev cyclone10 cycloneiv cycloneive
+families := max10 a10gx cyclonev cyclone10lp cycloneiv cycloneive
 $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
 $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
 #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))
diff --git a/techlibs/intel/cyclone10/cells_arith.v b/techlibs/intel/cyclone10lp/cells_arith.v
index 5ae8d6cea..5ae8d6cea 100644
--- a/techlibs/intel/cyclone10/cells_arith.v
+++ b/techlibs/intel/cyclone10lp/cells_arith.v
diff --git a/techlibs/intel/cyclone10/cells_map.v b/techlibs/intel/cyclone10lp/cells_map.v
index c2f6f403c..c2f6f403c 100644
--- a/techlibs/intel/cyclone10/cells_map.v
+++ b/techlibs/intel/cyclone10lp/cells_map.v
diff --git a/techlibs/intel/cyclone10/cells_sim.v b/techlibs/intel/cyclone10lp/cells_sim.v
index f5a8aee2b..f5a8aee2b 100644
--- a/techlibs/intel/cyclone10/cells_sim.v
+++ b/techlibs/intel/cyclone10lp/cells_sim.v
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index e5dc1adc7..5e6d2df2c 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -36,10 +36,10 @@ struct SynthIntelPass : public ScriptPass {
 		log("\n");
 		log("This command runs synthesis for Intel FPGAs.\n");
 		log("\n");
-		log("    -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
+		log("    -family <max10 | a10gx | cyclone10lp | cyclonev | cycloneiv | cycloneive>\n");
 		log("        generate the synthesis netlist for the specified family.\n");
 		log("        MAX10 is the default target if no family argument specified.\n");
-		log("        For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
+		log("        For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n");
 		log("        Cyclone V and Arria 10 GX devices are experimental.\n");
 		log("\n");
 		log("    -top <module>\n");
@@ -152,7 +152,7 @@ struct SynthIntelPass : public ScriptPass {
 		    family_opt != "cyclonev" &&
 		    family_opt != "cycloneiv" &&
 		    family_opt != "cycloneive" &&
-		    family_opt != "cyclone10")
+		    family_opt != "cyclone10lp")
 			log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str());
 
 		log_header(design, "Executing SYNTH_INTEL pass.\n");