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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-13 12:01:03 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-13 12:01:03 -0800 |
| commit | 52875b0d61b2b1cc83a9e9d51964a92027c3758c (patch) | |
| tree | bbcfea00583b78107498a01fe2a7cdbb48e41e2d /techlibs | |
| parent | 9ab1feeaf11adb6b675ac4034e246cb137d07db9 (diff) | |
| parent | 1c9634558747bf5b92a309b6af013a54034c35d3 (diff) | |
| download | yosys-52875b0d61b2b1cc83a9e9d51964a92027c3758c.tar.gz yosys-52875b0d61b2b1cc83a9e9d51964a92027c3758c.tar.bz2 yosys-52875b0d61b2b1cc83a9e9d51964a92027c3758c.zip | |
Merge pull request #1533 from dh73/bram_xilinx
Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/xc7_xcu_brams.txt | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index f1161114e..b7c893ff7 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -1,4 +1,3 @@ - bram $__XILINX_RAMB36_SDP init 1 abits 9 @@ -72,8 +71,13 @@ bram $__XILINX_RAMB18_TDP clkpol 2 3 endbram +# The "min bits" value were taken from: +# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), +# v1.14 ed., p 29-30, July, 2019. +# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf + match $__XILINX_RAMB36_SDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp @@ -81,7 +85,7 @@ match $__XILINX_RAMB36_SDP endmatch match $__XILINX_RAMB18_SDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp @@ -89,7 +93,7 @@ match $__XILINX_RAMB18_SDP endmatch match $__XILINX_RAMB36_TDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp @@ -97,9 +101,8 @@ match $__XILINX_RAMB36_TDP endmatch match $__XILINX_RAMB18_TDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp endmatch - |