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| author | Diego H <diego@symbioticeda.com> | 2019-11-26 17:14:41 -0600 |
|---|---|---|
| committer | Diego H <diego@symbioticeda.com> | 2019-11-27 12:05:04 -0600 |
| commit | 3a5a65829cc593965304537ddcb4d6d1d3e3ca8b (patch) | |
| tree | 9c542b58fa176cec05c76a2096d0285ff0f254c7 /techlibs | |
| parent | 0466c48533ad2831a95c6b63c3a190adb76499e9 (diff) | |
| download | yosys-3a5a65829cc593965304537ddcb4d6d1d3e3ca8b.tar.gz yosys-3a5a65829cc593965304537ddcb4d6d1d3e3ca8b.tar.bz2 yosys-3a5a65829cc593965304537ddcb4d6d1d3e3ca8b.zip | |
Adjusting Vivado's BRAM min bits threshold for RAMB18E1
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/xc7_xcu_brams.txt | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index f1161114e..ee961fff8 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -81,7 +81,7 @@ match $__XILINX_RAMB36_SDP endmatch match $__XILINX_RAMB18_SDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp @@ -97,9 +97,12 @@ match $__XILINX_RAMB36_TDP endmatch match $__XILINX_RAMB18_TDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp endmatch +# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), +# v1.14 ed., p 29-30, July, 2019. + |