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* DSP48E1 sim model: seq test workingDavid Shah2019-08-083-16/+60
* DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-082-8/+13
* [wip] sim model testingDavid Shah2019-08-084-15/+77
* [wip] sim model testingDavid Shah2019-08-083-40/+360
* [wip] DSP48E1 sim model improvementsDavid Shah2019-08-071-6/+82
* [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
* [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-8/+75
* Trim Y_WIDTHEddie Hung2019-08-011-5/+3
* Add DSP_SIGNEDONLY backEddie Hung2019-08-011-0/+16
* DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTHEddie Hung2019-08-012-5/+12
* Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
* Revert "Do not do sign extension in techmap; let packer do it"Eddie Hung2019-08-011-5/+14
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-016-18/+24
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| * RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
| * Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-254-5/+11
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| | * intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-234-5/+12
| * | Merge pull request #1218 from ZirconiumX/synth_intel_iopadsClifford Wolf2019-07-251-8/+8
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| | * | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
| * | | Merge pull request #1224 from YosysHQ/xilinx_fix_ffEddie Hung2019-07-251-2/+2
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| | * | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
* | | | Fix B_WIDTH > DSP_B_MAXWIDTH caseEddie Hung2019-08-011-32/+14
* | | | Do not compute sign bit if result is zeroEddie Hung2019-07-311-1/+2
* | | | For signed multipliers, compute sign bit separately...Eddie Hung2019-07-311-23/+42
* | | | Fix spacingEddie Hung2019-07-261-3/+3
* | | | Add copyright header, comment on cascadeEddie Hung2019-07-241-4/+34
* | | | Typo for Y_WIDTHEddie Hung2019-07-231-1/+1
* | | | Remove debugEddie Hung2019-07-221-1/+0
* | | | Rename according to vendor doc TN1295Eddie Hung2019-07-221-0/+1
* | | | opt and wreduce necessary for -dspEddie Hung2019-07-221-2/+4
* | | | Use minimum sized width wiresEddie Hung2019-07-221-7/+13
* | | | Indirection via $__soft_mulEddie Hung2019-07-192-9/+10
* | | | Do not do sign extension in techmap; let packer do itEddie Hung2019-07-191-14/+5
* | | | Do not $mul -> $__mul if A and B are less than maxwidthEddie Hung2019-07-191-1/+3
* | | | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this thresholdEddie Hung2019-07-191-1/+1
* | | | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 tooEddie Hung2019-07-191-28/+68
* | | | Merge branch 'xc7dsp' into ice40dspEddie Hung2019-07-191-1/+1
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| * | | | Fix typo in BEddie Hung2019-07-191-1/+1
| * | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1815-84/+164
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* | | | | Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dspEddie Hung2019-07-193-7/+239
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| * | | | ice40: Fix test_dsp_model.shDavid Shah2019-07-191-1/+1
| * | | | ice40/cells_sim.v: Fix sign of J and K partial productsDavid Shah2019-07-191-5/+7
| * | | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 modeDavid Shah2019-07-191-2/+2
| * | | | Add tests for all combinations of A and B signedness for comb mulEddie Hung2019-07-192-1/+229
| * | | | Don't copy ref if exists alreadyEddie Hung2019-07-191-1/+3
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* | | | Use sign_headroom insteadEddie Hung2019-07-191-4/+4
* | | | Fix SB_MAC sim model -- do not sign extend internal products?Eddie Hung2019-07-181-2/+2
* | | | Add paramsEddie Hung2019-07-181-0/+6
* | | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-181-33/+18
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| * | | Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
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| | * | | synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
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