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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-31 16:04:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-31 16:04:19 -0700 |
| commit | d2c33863d08bbc506888b723a304aa11f8650296 (patch) | |
| tree | ca103b236f00d675668215f0f34ef4971bcf43a5 /techlibs | |
| parent | 60c4887d15f89499d351fe9bd9ed36a5a4c1fe37 (diff) | |
| download | yosys-d2c33863d08bbc506888b723a304aa11f8650296.tar.gz yosys-d2c33863d08bbc506888b723a304aa11f8650296.tar.bz2 yosys-d2c33863d08bbc506888b723a304aa11f8650296.zip | |
Do not compute sign bit if result is zero
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index b745547a8..bfd216fbf 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -69,7 +69,6 @@ module \$mul (A, B, Y); );
else if (A_SIGNED && (A_WIDTH > `DSP_A_MAXWIDTH || B_WIDTH > `DSP_B_MAXWIDTH)) begin
wire _;
- assign Y[Y_WIDTH-1] = A[A_WIDTH-1] ^ B[B_WIDTH-1];
\$__mul #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
@@ -81,6 +80,8 @@ module \$mul (A, B, Y); .B(B),
.Y({_,Y[Y_WIDTH-2:0]})
);
+ // For non-zero results, recompute sign bit
+ assign Y[Y_WIDTH-1] = (|Y[Y_WIDTH-2:0]) & (A[A_WIDTH-1] ^ B[B_WIDTH-1]);
end
else
\$__mul #(
|