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* Fixed xilinx FDSE sim modelClifford Wolf2015-01-241-2/+2
* Added $equiv cell typeClifford Wolf2015-01-191-1/+23
* Various cleanups in xilinx techlibClifford Wolf2015-01-187-9/+110
* Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-183-468/+55
* Added synth_xilinx -retime -flattenClifford Wolf2015-01-171-2/+28
* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-174-2/+106
* Added cells.libClifford Wolf2015-01-162-0/+109
* Added dff2dffe to synth_xilinxClifford Wolf2015-01-161-0/+2
* Added more FF types to xilinx/cells.vClifford Wolf2015-01-161-25/+28
* Fixed xilinx bram clock inverted configClifford Wolf2015-01-161-21/+35
* Added FF cells to xilinx/cells_sim.vClifford Wolf2015-01-161-116/+116
* Added Xilinx MUXF7 and MUXF8 supportClifford Wolf2015-01-152-2/+30
* Various cleanups in synth_xilinx commandClifford Wolf2015-01-131-54/+8
* Added add_share_file Makefile macroClifford Wolf2015-01-082-38/+10
* added minimalistic xilinx sim modelsClifford Wolf2015-01-081-0/+150
* More Xilinx bram cleanupsClifford Wolf2015-01-071-14/+14
* Cleanups in xilinx bram descriptionsClifford Wolf2015-01-072-36/+36
* Xilinx RAMB36/RAMB18 memory_bram support completeClifford Wolf2015-01-063-16/+320
* Towards Xilinx bram supportClifford Wolf2015-01-063-24/+65
* small fix in xilinx/brams.vClifford Wolf2015-01-061-5/+5
* Towards Xilinx bram supportClifford Wolf2015-01-064-25/+176
* Various small improvements to synth_xilinxClifford Wolf2015-01-061-8/+6
* Towards Xilinx bram supportClifford Wolf2015-01-062-13/+41
* Towards Xilinx bram supportClifford Wolf2015-01-063-6/+10
* Towards Xilinx bram supportClifford Wolf2015-01-057-19/+172
* Towards Xilinx bram supportClifford Wolf2015-01-043-13/+182
* Progress in memory_bramClifford Wolf2015-01-031-0/+3
* Added proper clkpol support to memory_bramClifford Wolf2015-01-021-1/+1
* New $mem simlib modelClifford Wolf2015-01-021-95/+36
* Progress in memory_bramClifford Wolf2014-12-311-3/+3
* Added memory_bram (not functional yet)Clifford Wolf2014-12-311-0/+20
* Fixed simlib entries for $memrd and $memwrClifford Wolf2014-12-301-0/+2
* Fixed build with SMALL=1Clifford Wolf2014-12-301-0/+2
* Improvements in simplemap api, added $ne $nex $eq $eqx supportClifford Wolf2014-12-241-49/+5
* Removed UTF-8 chars from techmap.vClifford Wolf2014-12-121-1/+1
* Added $dffe cell typeClifford Wolf2014-12-082-1/+20
* Added $_DFFE_??_ cell typesClifford Wolf2014-12-081-0/+32
* Added "abc" label in synth scriptClifford Wolf2014-10-311-6/+12
* Added "opt -full" alias for all more aggressive optimizationsClifford Wolf2014-10-311-2/+6
* Added $_BUF_ cell typeClifford Wolf2014-10-031-0/+6
* namespace YosysClifford Wolf2014-09-272-2/+10
* Improvements in "synth" scriptClifford Wolf2014-09-181-8/+12
* Fixed $macc simlib model for zero-configClifford Wolf2014-09-161-1/+1
* Added "synth" commandClifford Wolf2014-09-142-0/+154
* Using alumacc in techmap.vClifford Wolf2014-09-141-237/+33
* Fixed simlib $macc model for xilinx xsimClifford Wolf2014-09-081-1/+15
* Simplified $fa undef modelClifford Wolf2014-09-081-1/+1
* Fixes and cleanups for blackbox.vClifford Wolf2014-09-082-70/+73
* Added $lcu cell typeClifford Wolf2014-09-082-74/+31
* Added "$fa" cell typeClifford Wolf2014-09-082-0/+28
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