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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-15 13:50:04 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-15 13:50:04 +0100 |
| commit | b197279f3c2d7b487d69cafca8dfc5edb4b2eaa8 (patch) | |
| tree | 79a58ee5a1f8595b769426faca666c43da9949da /techlibs | |
| parent | 2e36faeced76fe0a4d19a1febddd070263955034 (diff) | |
| download | yosys-b197279f3c2d7b487d69cafca8dfc5edb4b2eaa8.tar.gz yosys-b197279f3c2d7b487d69cafca8dfc5edb4b2eaa8.tar.bz2 yosys-b197279f3c2d7b487d69cafca8dfc5edb4b2eaa8.zip | |
Added Xilinx MUXF7 and MUXF8 support
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells.v | 28 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
2 files changed, 30 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells.v b/techlibs/xilinx/cells.v index d19be0db7..75253f57b 100644 --- a/techlibs/xilinx/cells.v +++ b/techlibs/xilinx/cells.v @@ -45,6 +45,34 @@ module \$lut (A, Y); LUT6 #(.INIT(LUT)) fpga_lut (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .I4(A[4]), .I5(A[5])); + end else + if (WIDTH == 7) begin:lut7 + wire T0, T1; + LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); + LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); + MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6])); + end else + if (WIDTH == 8) begin:lut8 + wire T0, T1, T2, T3, T4, T5; + LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); + LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); + LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); + LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); + MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6])); + MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6])); + MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7])); end else begin:error wire _TECHMAP_FAIL_ = 1; end diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e7308461a..380fdae73 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -75,7 +75,7 @@ struct SynthXilinxPass : public Pass { log(" synth -run fine\n"); log("\n"); log(" map_luts:\n"); - log(" abc -lut 6\n"); + log(" abc -lut 6:8\n"); log(" clean\n"); log("\n"); log(" map_cells:\n"); @@ -147,7 +147,7 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "map_luts")) { - Pass::call(design, "abc -lut 6"); + Pass::call(design, "abc -lut 6:8"); Pass::call(design, "clean"); } |