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Author
Age
Files
Lines
*
Added iCE40 PLL cells
Clifford Wolf
2015-05-31
1
-0
/
+168
*
Added output args to synth_ice40
Clifford Wolf
2015-05-26
2
-2
/
+37
*
improved ice40 SB_IO sim model
Clifford Wolf
2015-05-23
1
-16
/
+9
*
Added ice40 SB_IO sim model
Clifford Wolf
2015-05-23
1
-1
/
+46
*
Verific build fixes
Clifford Wolf
2015-05-17
2
-4
/
+4
*
ice40_opt bugfix
Clifford Wolf
2015-04-27
2
-6
/
+4
*
iCE40: SB_CARRY const fold -> unmap SB_LUT
Clifford Wolf
2015-04-27
1
-3
/
+44
*
Added simplemap $lut support
Clifford Wolf
2015-04-27
1
-8
/
+2
*
Added iCE40 const folding support for SB_CARRY
Clifford Wolf
2015-04-27
3
-2
/
+134
*
Initialization support for all iCE40 bram modes
Clifford Wolf
2015-04-26
8
-28
/
+65
*
initialized iCE40 brams (mode 0)
Clifford Wolf
2015-04-25
5
-54
/
+261
*
improved iCE40 SB_RAM40_4K simulation model
Clifford Wolf
2015-04-25
1
-59
/
+83
*
More iCE40 bram improvements
Clifford Wolf
2015-04-25
4
-51
/
+69
*
iCE40 bram progress
Clifford Wolf
2015-04-24
2
-16
/
+35
*
iCE40 bram tests and fixes
Clifford Wolf
2015-04-24
6
-16
/
+181
*
Added ice40 bram support
Clifford Wolf
2015-04-24
4
-1
/
+192
*
iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models
Clifford Wolf
2015-04-19
1
-13
/
+289
*
added sync reset to ice40 test_ffs.sh
Clifford Wolf
2015-04-18
3
-6
/
+20
*
Added ice40 test_arith
Clifford Wolf
2015-04-18
2
-0
/
+13
*
Added ice40 SB_CARRY support
Clifford Wolf
2015-04-18
3
-2
/
+81
*
Added mapping of synchronous set/reset to iCE40 flow
Clifford Wolf
2015-04-17
3
-4
/
+130
*
Changed ice40 ICESTORM_CARRYCONST port name
Clifford Wolf
2015-04-16
1
-2
/
+2
*
Fixed "dff2dffe -direct-match"
Clifford Wolf
2015-04-16
1
-0
/
+2
*
Added simple ice40 dff tests
Clifford Wolf
2015-04-16
3
-0
/
+49
*
improved ice40 dff cell mapping
Clifford Wolf
2015-04-16
3
-7
/
+46
*
use "hierarchy -auto-top" in synth_ice40
Clifford Wolf
2015-04-14
1
-3
/
+3
*
more cells in ice40 cell library
Clifford Wolf
2015-04-14
1
-8
/
+289
*
Improved xilinx "bram1" test
Clifford Wolf
2015-04-09
1
-1
/
+2
*
Added memory_bram "make_outreg" feature
Clifford Wolf
2015-04-09
1
-0
/
+2
*
Xilinx DRAMS: RAM64X1D, RAM128X1D
Clifford Wolf
2015-04-09
3
-13
/
+67
*
Towards DRAM support in Xilinx flow
Clifford Wolf
2015-04-09
5
-0
/
+78
*
Added support for initialized xilinx brams
Clifford Wolf
2015-04-06
10
-91
/
+314
*
Added Xilinx test case for initialized brams
Clifford Wolf
2015-04-06
4
-0
/
+80
*
Added Xilinx bram black-box modules
Clifford Wolf
2015-04-06
3
-0
/
+322
*
make all vector-size related integer params in $mem sim model signed
Clifford Wolf
2015-04-05
1
-6
/
+6
*
Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
Clifford Wolf
2015-04-05
1
-0
/
+29
*
Added "dffinit", Support for initialized Xilinx DFF
Clifford Wolf
2015-04-04
1
-5
/
+6
*
Fixes in cmos_cells.v
Clifford Wolf
2015-03-25
1
-3
/
+12
*
Added very first version of "synth_ice40"
Clifford Wolf
2015-03-05
4
-0
/
+211
*
Added $assume cell type
Clifford Wolf
2015-02-26
1
-1
/
+18
*
Added "stat" to "synth" and "synth_xilinx"
Clifford Wolf
2015-02-15
2
-0
/
+4
*
Added final checks to "synth" and "synth_xilinx"
Clifford Wolf
2015-02-15
2
-7
/
+24
*
Smaller default parameters in $mem simlib model
Clifford Wolf
2015-02-15
1
-2
/
+2
*
Added $meminit support to "memory" command
Clifford Wolf
2015-02-14
1
-3
/
+15
*
Added $meminit cell type
Clifford Wolf
2015-02-14
1
-0
/
+22
*
Added "check" command
Clifford Wolf
2015-02-13
1
-0
/
+4
*
Some test related fixes
Clifford Wolf
2015-02-12
1
-4
/
+4
*
Disabled (unused) Xilinx tristate buffers
Clifford Wolf
2015-02-04
1
-6
/
+6
*
no support for 6-series xilinx devices
Clifford Wolf
2015-02-01
1
-1
/
+1
*
Removed old XST-based xilinx examples
Clifford Wolf
2015-02-01
11
-208
/
+0
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