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author | Clifford Wolf <clifford@clifford.at> | 2015-02-01 23:06:44 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-02-01 23:06:44 +0100 |
commit | bebbf2e5a4ca6a1378f621243dfc06b185a6884e (patch) | |
tree | 6666337237318fb27ca6fc49fbdc2bc050b6dc11 /techlibs | |
parent | 893fe87a33dc6646cabc7538d4dbe411041afb94 (diff) | |
download | yosys-bebbf2e5a4ca6a1378f621243dfc06b185a6884e.tar.gz yosys-bebbf2e5a4ca6a1378f621243dfc06b185a6884e.tar.bz2 yosys-bebbf2e5a4ca6a1378f621243dfc06b185a6884e.zip |
no support for 6-series xilinx devices
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index caa7e205d..7812fa290 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -44,7 +44,7 @@ struct SynthXilinxPass : public Pass { log("\n"); log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n"); log("partly selected designs. At the moment this command creates netlists that are\n"); - log("compatible with 7-series and 6-series Xilinx devices.\n"); + log("compatible with 7-Series Xilinx devices.\n"); log("\n"); log(" -top <module>\n"); log(" use the specified module as top module (default='top')\n"); |