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| author | Clifford Wolf <clifford@clifford.at> | 2015-03-25 09:00:41 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-03-25 09:00:41 +0100 |
| commit | e468d4cc6001b65b9c7e72d3f9c0e9b939ad31b9 (patch) | |
| tree | 3032533c772ac8787622b7b6d6deb21e42e5c0da /techlibs | |
| parent | 68bbb15214e0048e4f32e0c38e192eab62dea7bd (diff) | |
| download | yosys-e468d4cc6001b65b9c7e72d3f9c0e9b939ad31b9.tar.gz yosys-e468d4cc6001b65b9c7e72d3f9c0e9b939ad31b9.tar.bz2 yosys-e468d4cc6001b65b9c7e72d3f9c0e9b939ad31b9.zip | |
Fixes in cmos_cells.v
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/cmos/cmos_cells.v | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/techlibs/cmos/cmos_cells.v b/techlibs/cmos/cmos_cells.v index da75270cb..27278facb 100644 --- a/techlibs/cmos/cmos_cells.v +++ b/techlibs/cmos/cmos_cells.v @@ -1,17 +1,26 @@ +module BUF(A, Y); +input A; +output Y; +assign Y = A; +endmodule + module NOT(A, Y); input A; -output Y = ~A; +output Y; +assign Y = ~A; endmodule module NAND(A, B, Y); input A, B; -output Y = ~(A & B); +output Y; +assign Y = ~(A & B); endmodule module NOR(A, B, Y); input A, B; -output Y = ~(A | B); +output Y; +assign Y = ~(A | B); endmodule module DFF(C, D, Q); |