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author | Clifford Wolf <clifford@clifford.at> | 2015-02-01 17:10:46 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-02-01 17:10:46 +0100 |
commit | 3cbfa3815ee0c40fcafe80d56afec97c36368f06 (patch) | |
tree | 4f1ccade1714d31d8bb1443b4a1735a3174f0492 /techlibs | |
parent | 816fe6bbe0ad90f7a696dd208dae6db8139dfd00 (diff) | |
download | yosys-3cbfa3815ee0c40fcafe80d56afec97c36368f06.tar.gz yosys-3cbfa3815ee0c40fcafe80d56afec97c36368f06.tar.bz2 yosys-3cbfa3815ee0c40fcafe80d56afec97c36368f06.zip |
Removed old XST-based xilinx examples
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/xilinx/example_mojo_counter/README | 10 | ||||
-rw-r--r-- | techlibs/xilinx/example_mojo_counter/example.sh | 18 | ||||
-rw-r--r-- | techlibs/xilinx/example_mojo_counter/example.ucf | 14 | ||||
-rw-r--r-- | techlibs/xilinx/example_mojo_counter/example.v | 14 | ||||
-rw-r--r-- | techlibs/xilinx/example_sim_counter/counter.v | 12 | ||||
-rw-r--r-- | techlibs/xilinx/example_sim_counter/counter_tb.v | 61 | ||||
-rw-r--r-- | techlibs/xilinx/example_sim_counter/run_sim.sh | 23 | ||||
-rw-r--r-- | techlibs/xilinx/example_zed_counter/README | 10 | ||||
-rw-r--r-- | techlibs/xilinx/example_zed_counter/example.sh | 18 | ||||
-rw-r--r-- | techlibs/xilinx/example_zed_counter/example.ucf | 14 | ||||
-rw-r--r-- | techlibs/xilinx/example_zed_counter/example.v | 14 |
11 files changed, 0 insertions, 208 deletions
diff --git a/techlibs/xilinx/example_mojo_counter/README b/techlibs/xilinx/example_mojo_counter/README deleted file mode 100644 index 690a9d843..000000000 --- a/techlibs/xilinx/example_mojo_counter/README +++ /dev/null @@ -1,10 +0,0 @@ - -This is a simple example for Yosys synthesis targeting the Mojo FPGA -development board [1, 2]. Simple script for xst-based synthesis (incl. -generation of reference edif files) and uploading to the board can be -found here [3]. - -[1] http://embeddedmicro.com/tutorials/mojo -[2] https://www.sparkfun.com/products/11953 -[3] http://svn.clifford.at/handicraft/2013/mojo/ - diff --git a/techlibs/xilinx/example_mojo_counter/example.sh b/techlibs/xilinx/example_mojo_counter/example.sh deleted file mode 100644 index 74a0c117f..000000000 --- a/techlibs/xilinx/example_mojo_counter/example.sh +++ /dev/null @@ -1,18 +0,0 @@ -#!/bin/bash - -set -ex - -XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE -XILINX_PART=xc6slx9-2-tqg144 - -../../../yosys - <<- EOT - read_verilog example.v - synth_xilinx -edif synth.edif -EOT - -$XILINX_DIR/bin/lin64/edif2ngd -a synth.edif synth.ngo -$XILINX_DIR/bin/lin64/ngdbuild -p $XILINX_PART -uc example.ucf synth.ngo synth.ngd -$XILINX_DIR/bin/lin64/map -p $XILINX_PART -w -o mapped.ncd synth.ngd constraints.pcf -$XILINX_DIR/bin/lin64/par -w mapped.ncd placed.ncd constraints.pcf -$XILINX_DIR/bin/lin64/bitgen -w placed.ncd example.bit constraints.pcf - diff --git a/techlibs/xilinx/example_mojo_counter/example.ucf b/techlibs/xilinx/example_mojo_counter/example.ucf deleted file mode 100644 index 93d97b4dc..000000000 --- a/techlibs/xilinx/example_mojo_counter/example.ucf +++ /dev/null @@ -1,14 +0,0 @@ -NET "clk" TNM_NET = clk; -TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%; - -NET "clk" LOC = P56; -NET "ctrl" LOC = P1; - -NET "led_0" LOC = P134; -NET "led_1" LOC = P133; -NET "led_2" LOC = P132; -NET "led_3" LOC = P131; -NET "led_4" LOC = P127; -NET "led_5" LOC = P126; -NET "led_6" LOC = P124; -NET "led_7" LOC = P123; diff --git a/techlibs/xilinx/example_mojo_counter/example.v b/techlibs/xilinx/example_mojo_counter/example.v deleted file mode 100644 index cb98cc1b2..000000000 --- a/techlibs/xilinx/example_mojo_counter/example.v +++ /dev/null @@ -1,14 +0,0 @@ -module top(clk, ctrl, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0); - -input clk, ctrl; -output led_7, led_6, led_5, led_4; -output led_3, led_2, led_1, led_0; - -reg [31:0] counter; - -always @(posedge clk) - counter <= counter + (ctrl ? 4 : 1); - -assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24; - -endmodule diff --git a/techlibs/xilinx/example_sim_counter/counter.v b/techlibs/xilinx/example_sim_counter/counter.v deleted file mode 100644 index 72208bd80..000000000 --- a/techlibs/xilinx/example_sim_counter/counter.v +++ /dev/null @@ -1,12 +0,0 @@ -module counter (clk, rst, en, count); - - input clk, rst, en; - output reg [3:0] count; - - always @(posedge clk) - if (rst) - count <= 4'd0; - else if (en) - count <= count + 4'd1; - -endmodule diff --git a/techlibs/xilinx/example_sim_counter/counter_tb.v b/techlibs/xilinx/example_sim_counter/counter_tb.v deleted file mode 100644 index b6b64269e..000000000 --- a/techlibs/xilinx/example_sim_counter/counter_tb.v +++ /dev/null @@ -1,61 +0,0 @@ -`timescale 1 ns / 1 ps - -module testbench; - -reg clk, en, rst; -wire [3:0] count; - -counter uut_counter( - .clk(clk), - .count(count), - .en(en), - .rst(rst) -); - -initial begin - clk <= 0; - forever begin - #50; - clk <= ~clk; - end -end - -initial begin - @(posedge clk); - forever begin - @(posedge clk); - $display("%d", count); - end -end - -initial begin - rst <= 1; en <= 0; @(posedge clk); - rst <= 1; en <= 0; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 1; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 1; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - $finish; -end - -endmodule diff --git a/techlibs/xilinx/example_sim_counter/run_sim.sh b/techlibs/xilinx/example_sim_counter/run_sim.sh deleted file mode 100644 index b8354c002..000000000 --- a/techlibs/xilinx/example_sim_counter/run_sim.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/bash - -set -ex - -XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE - -../../../yosys -p 'synth_xilinx -top counter; write_verilog -noattr testbench_synth.v' counter.v - -iverilog -o testbench_gold counter_tb.v counter.v -iverilog -o testbench_gate counter_tb.v testbench_synth.v \ - $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6,BUFGP,IBUF}}.v - -./testbench_gold > testbench_gold.txt -./testbench_gate > testbench_gate.txt - -if diff -u testbench_gold.txt testbench_gate.txt; then - set +x; echo; echo; banner " PASS " -else - exit 1 -fi - -rm -f testbench_{synth,gold,gate,mapped}* - diff --git a/techlibs/xilinx/example_zed_counter/README b/techlibs/xilinx/example_zed_counter/README deleted file mode 100644 index 539f24e73..000000000 --- a/techlibs/xilinx/example_zed_counter/README +++ /dev/null @@ -1,10 +0,0 @@ - -This is a simple example for Yosys synthesis targeting the ZED FPGA -development board [1, 2]. Simple script for xst-based synthesis (incl. -generation of reference edif files) and uploading to the board can be -found here [3]. - -[1] http://www.zedboard.org/ -[2] https://www.xilinx.com/zynq/ -[3] http://verilog.james.walms.co.uk/ - diff --git a/techlibs/xilinx/example_zed_counter/example.sh b/techlibs/xilinx/example_zed_counter/example.sh deleted file mode 100644 index d0fcd8322..000000000 --- a/techlibs/xilinx/example_zed_counter/example.sh +++ /dev/null @@ -1,18 +0,0 @@ -#!/bin/bash - -set -ex - -XILINX_DIR=/opt/Xilinx/14.7/ISE_DS/ISE -XILINX_PART=xc7z020clg484-1 - -yosys - <<- EOT - read_verilog example.v - synth_xilinx -edif synth.edif -EOT - -$XILINX_DIR/bin/lin64/edif2ngd -a synth.edif synth.ngo -$XILINX_DIR/bin/lin64/ngdbuild -p $XILINX_PART -uc example.ucf synth.ngo synth.ngd -$XILINX_DIR/bin/lin64/map -p $XILINX_PART -w -o mapped.ncd synth.ngd constraints.pcf -$XILINX_DIR/bin/lin64/par -w mapped.ncd placed.ncd constraints.pcf -$XILINX_DIR/bin/lin64/bitgen -w placed.ncd example.bit constraints.pcf -$XILINX_DIR/bin/lin64/promgen -w -b -p bin -o example.bin -u 0 example.bit -data_width 32 diff --git a/techlibs/xilinx/example_zed_counter/example.ucf b/techlibs/xilinx/example_zed_counter/example.ucf deleted file mode 100644 index dadc8373c..000000000 --- a/techlibs/xilinx/example_zed_counter/example.ucf +++ /dev/null @@ -1,14 +0,0 @@ -NET "clk" TNM_NET = clk; -TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%; - -NET "clk" LOC = Y9 | IOSTANDARD=LVCMOS33; # "GCLK" -NET "ctrl" LOC = P16 | IOSTANDARD=LVCMOS18; # "BTNC" - -NET "led_0" LOC = T22 | IOSTANDARD=LVCMOS33; # "LD0" -NET "led_1" LOC = T21 | IOSTANDARD=LVCMOS33; # "LD0" -NET "led_2" LOC = U22 | IOSTANDARD=LVCMOS33; # "LD0" -NET "led_3" LOC = U21 | IOSTANDARD=LVCMOS33; # "LD0" -NET "led_4" LOC = V22 | IOSTANDARD=LVCMOS33; # "LD0" -NET "led_5" LOC = W22 | IOSTANDARD=LVCMOS33; # "LD0" -NET "led_6" LOC = U19 | IOSTANDARD=LVCMOS33; # "LD0" -NET "led_7" LOC = U14 | IOSTANDARD=LVCMOS33; # "LD0" diff --git a/techlibs/xilinx/example_zed_counter/example.v b/techlibs/xilinx/example_zed_counter/example.v deleted file mode 100644 index cb98cc1b2..000000000 --- a/techlibs/xilinx/example_zed_counter/example.v +++ /dev/null @@ -1,14 +0,0 @@ -module top(clk, ctrl, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0); - -input clk, ctrl; -output led_7, led_6, led_5, led_4; -output led_3, led_2, led_1, led_0; - -reg [31:0] counter; - -always @(posedge clk) - counter <= counter + (ctrl ? 4 : 1); - -assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24; - -endmodule |