| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-23 | 17 | -102/+981 |
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| | * | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 |
| | * | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 3 | -14/+28 |
| | * | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | * | Merge pull request #1289 from mmicko/anlogic_fixes | Clifford Wolf | 2019-08-22 | 5 | -91/+162 |
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| | | * | Merge remote-tracking branch 'upstream/master' into anlogic_fixes | Miodrag Milanovic | 2019-08-18 | 7 | -165/+37 |
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| | | * | | Proper arith for Anlogic and use standard pass | Miodrag Milanovic | 2019-08-12 | 5 | -91/+162 |
| | * | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | * | | | Merge pull request #1281 from mmicko/efinix | Clifford Wolf | 2019-08-22 | 9 | -0/+798 |
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| | | * | | | Fix formating | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 |
| | | * | | | one bit enable signal | Miodrag Milanovic | 2019-08-11 | 1 | -1/+1 |
| | | * | | | fix mixing signals on FF mapping | Miodrag Milanovic | 2019-08-11 | 1 | -4/+4 |
| | | * | | | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 3 | -91/+1 |
| | | * | | | Fixed data width | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 |
| | | * | | | Adding new pass to fix carry chain | Miodrag Milanovic | 2019-08-11 | 3 | -0/+124 |
| | | * | | | cleanup | Miodrag Milanovic | 2019-08-11 | 1 | -4/+7 |
| | | * | | | Fix CO | Miodrag Milanovic | 2019-08-09 | 1 | -26/+24 |
| | | * | | | Merge remote-tracking branch 'upstream/master' into efinix | Miodrag Milanovic | 2019-08-09 | 9 | -267/+303 |
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| | | * | | | | clock for ram trough gbuf | Miodrag Milanovic | 2019-08-04 | 1 | -0/+6 |
| | | * | | | | Added bram support | Miodrag Milanovic | 2019-08-04 | 6 | -1/+260 |
| | | * | | | | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 4 | -1/+129 |
| | | * | | | | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 5 | -0/+370 |
| * | | | | | | Use semicolon | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
| * | | | | | | techmap before read | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
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| | * | | | | | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
| * | | | | | | Add abc_arrival to SRL* | Eddie Hung | 2019-08-21 | 1 | -3/+5 |
| * | | | | | | Oops | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
| * | | | | | | xilinx to use abc_map.v with -max_iter 1 | Eddie Hung | 2019-08-20 | 6 | -171/+26 |
| * | | | | | | ecp5: remove DPR16X4 from abc_unmap.v | Eddie Hung | 2019-08-20 | 1 | -20/+0 |
| * | | | | | | ecp5 to use -max_iter 1 | Eddie Hung | 2019-08-20 | 3 | -4/+3 |
| * | | | | | | ecp5 to use abc_map.v and _unmap.v | Eddie Hung | 2019-08-20 | 7 | -14/+89 |
| * | | | | | | Add reference to FD* timing | Eddie Hung | 2019-08-20 | 1 | -0/+2 |
| * | | | | | | Remove sequential extension | Eddie Hung | 2019-08-20 | 6 | -359/+17 |
| * | | | | | | Remove SRL* delays from cells_sim.v | Eddie Hung | 2019-08-20 | 1 | -5/+3 |
| * | | | | | | LUTMUX -> LUTMUX6 | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
| * | | | | | | Cleanup techmap in map_luts | Eddie Hung | 2019-08-20 | 1 | -3/+5 |
| * | | | | | | Move `techmap abc_map.v` into map_luts | Eddie Hung | 2019-08-20 | 1 | -1/+2 |
| * | | | | | | Remove delays from abc_map.v | Eddie Hung | 2019-08-20 | 1 | -5/+2 |
| * | | | | | | Typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 4 | -16/+19 |
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| | * | | | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 4 | -16/+19 |
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| | | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 26 | -343/+629 |
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| | | * | | | | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 |
| | | * | | | | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 |
| * | | | | | | | Wrap SRL{16,32} too | Eddie Hung | 2019-08-20 | 3 | -7/+98 |
| * | | | | | | | Wrap LUTRAMs in order to capture comb/seq behaviour | Eddie Hung | 2019-08-20 | 5 | -36/+200 |
| * | | | | | | | Add LUTRAM delays | Eddie Hung | 2019-08-20 | 1 | -3/+6 |
| * | | | | | | | Remove mapping rules | Eddie Hung | 2019-08-20 | 1 | -33/+0 |
| * | | | | | | | Remove -icells | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
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index : iCE40/yosys | |
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