| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Use semicolon | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
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| * | techmap before read | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
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| * | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
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| | * | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| * | | Add abc_arrival to SRL* | Eddie Hung | 2019-08-21 | 1 | -3/+5 |
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| * | | Oops | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| * | | xilinx to use abc_map.v with -max_iter 1 | Eddie Hung | 2019-08-20 | 6 | -171/+26 |
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| * | | ecp5: remove DPR16X4 from abc_unmap.v | Eddie Hung | 2019-08-20 | 1 | -20/+0 |
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| * | | ecp5 to use -max_iter 1 | Eddie Hung | 2019-08-20 | 3 | -4/+3 |
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| * | | ecp5 to use abc_map.v and _unmap.v | Eddie Hung | 2019-08-20 | 7 | -14/+89 |
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| * | | Add reference to FD* timing | Eddie Hung | 2019-08-20 | 1 | -0/+2 |
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| * | | Remove sequential extension | Eddie Hung | 2019-08-20 | 6 | -359/+17 |
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| * | | Remove SRL* delays from cells_sim.v | Eddie Hung | 2019-08-20 | 1 | -5/+3 |
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| * | | LUTMUX -> LUTMUX6 | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
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| * | | Cleanup techmap in map_luts | Eddie Hung | 2019-08-20 | 1 | -3/+5 |
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| * | | Move `techmap abc_map.v` into map_luts | Eddie Hung | 2019-08-20 | 1 | -1/+2 |
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| * | | Remove delays from abc_map.v | Eddie Hung | 2019-08-20 | 1 | -5/+2 |
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| * | | Typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 4 | -16/+19 |
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| | * | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 4 | -16/+19 |
| | |\ | | | | | | | [WIP] synth xilinx renaming, as per #1184 | ||||
| | | * | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 26 | -343/+629 |
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| | | * | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 |
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| | | * | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 |
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| * | | | | Wrap SRL{16,32} too | Eddie Hung | 2019-08-20 | 3 | -7/+98 |
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| * | | | | Wrap LUTRAMs in order to capture comb/seq behaviour | Eddie Hung | 2019-08-20 | 5 | -36/+200 |
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| * | | | | Add LUTRAM delays | Eddie Hung | 2019-08-20 | 1 | -3/+6 |
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| * | | | | Remove mapping rules | Eddie Hung | 2019-08-20 | 1 | -33/+0 |
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| * | | | | Remove -icells | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
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| * | | | | Use abc_{map,unmap,model}.v | Eddie Hung | 2019-08-20 | 7 | -110/+324 |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 3 | -6/+6 |
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| | * | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 3 | -19/+41 |
| | |\ \ \ | | |_|/ | |/| | | Refactor abc9 to use port attributes, not module attributes | ||||
| | | * | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 3 | -6/+6 |
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| * | | | | Add arrival times for SRL outputs | Eddie Hung | 2019-08-19 | 1 | -3/+5 |
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| * | | | | Add BRAM arrival times | Eddie Hung | 2019-08-19 | 1 | -8/+10 |
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| * | | | | Add reference to source of Tclktoq timing | Eddie Hung | 2019-08-19 | 1 | -0/+2 |
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| * | | | | Add 'abc_arrival' attribute for flop outputs | Eddie Hung | 2019-08-19 | 1 | -6/+6 |
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| * | | | | Update box timings | Eddie Hung | 2019-08-19 | 1 | -6/+9 |
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| * | | | | Move from cell attr to module attr | Eddie Hung | 2019-08-19 | 1 | -12/+6 |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-19 | 7 | -165/+37 |
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| | * | | | Merge branch 'master' into eddie/pr1266_again | whitequark | 2019-08-18 | 1 | -15/+5 |
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| | | * \ \ | Merge pull request #1250 from bwidawsk/master | Eddie Hung | 2019-08-16 | 1 | -15/+5 |
| | | |\ \ \ | | | | | | | | | | | | | techlibs/intel: Clean up Makefile | ||||
| | | | * | | | techlibs/intel: Clean up Makefile | Ben Widawsky | 2019-08-05 | 1 | -15/+5 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use GNU make's foreach iterator and remove nonexistent files. Gmake is already a requirement of the build system. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| | * | | | | | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-12 | 1 | -1/+1 |
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| | * | | | | | Revert "Merge pull request #1280 from ↵ | Eddie Hung | 2019-08-12 | 6 | -150/+32 |
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f. | ||||
| * | | | | | Use attributes instead of params | Eddie Hung | 2019-08-19 | 1 | -30/+12 |
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| * | | | | | Merge branch 'eddie/abc9_refactor' into xaig_dff | Eddie Hung | 2019-08-16 | 41 | -297/+1397 |
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| | * | | | | Update abc_* attr in ecp5 and ice40 | Eddie Hung | 2019-08-16 | 2 | -11/+21 |
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| | * | | | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules | Eddie Hung | 2019-08-16 | 1 | -8/+20 |
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| | * | | | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" | David Shah | 2019-08-10 | 6 | -32/+150 |
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| | * | | | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 5 | -20/+14 |
| | |\ \ \ | | | | | | | | | | | Cleanup a few barnacles across codebase | ||||
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index : iCE40/yosys | |
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