iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	xilinx: Add keep attribute where appropriate	David Shah	2019-03-22	2	-25/+31
*	Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873	Clifford Wolf	2019-03-19	1	-2/+4
*	Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes	Clifford Wolf	2019-03-12	1	-19/+0
*	Fix typo in ice40_braminit help msg	Clifford Wolf	2019-03-09	1	-1/+1
*	Merge pull request #859 from smunaut/ice40_braminit	Clifford Wolf	2019-03-09	4	-37/+212
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\| *	ice40: Run ice40_braminit pass by default	Sylvain Munaut	2019-03-08	1	-0/+1
\| *	ice40: Add ice40_braminit pass to allow initialization of BRAM from file	Sylvain Munaut	2019-03-08	3	-37/+211
* \|	Add link to SF2 / igloo2 macro library guide	Clifford Wolf	2019-03-07	1	-21/+24
* \|	Improvements in sf2 cells_sim.v	Clifford Wolf	2019-03-06	2	-30/+251
* \|	Add sf2 techmap rules for more FF types	Clifford Wolf	2019-03-06	1	-25/+39
* \|	Refactor SF2 iobuf insertion, Add clkint insertion	Clifford Wolf	2019-03-06	3	-83/+152
* \|	Improvements in SF2 flow and demo	Clifford Wolf	2019-03-05	2	-8/+23
* \|	Merge pull request #842 from litghost/merge_upstream	Clifford Wolf	2019-03-05	10	-176/+570
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\| * \|	Revert BRAM WRITE_MODE changes.	Keith Rothman	2019-03-04	1	-12/+12
\| * \|	Revert FF models to include IS_x_INVERTED parameters.	Keith Rothman	2019-03-01	1	-6/+34
\| * \|	Use singular for disabling of DRAM or BRAM inference.	Keith Rothman	2019-03-01	1	-13/+13
\| * \|	Modify arguments to match existing style.	Keith Rothman	2019-03-01	1	-6/+6
\| * \|	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	11	-221/+587
* \| \|	Merge pull request #850 from daveshah1/ecp5_warn_conflict	Clifford Wolf	2019-03-05	1	-2/+7
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\| * \| \|	ecp5: Demote conflicting FF init values to a warning	David Shah	2019-03-04	1	-2/+7
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* / /	Use "write_edif -pvector bra" for Xilinx EDIF files	Clifford Wolf	2019-03-05	1	-1/+1
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* \|	Fix ECP5 cells_sim for iverilog	Miodrag Milanovic	2019-03-01	1	-2/+3
* \|	Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode	Clifford Wolf	2019-02-28	1	-2/+2
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\| * \|	ice40: use 2 bits for READ/WRITE MODE for SB_RAM map	Elms	2019-02-28	1	-2/+2
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* \|	Reduce amount of trailing whitespace in code base	Larry Doolittle	2019-02-28	6	-19/+19
* \|	Merge pull request #794 from daveshah1/ecp5improve	Clifford Wolf	2019-02-28	7	-12/+388
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\| *	ecp5: Compatibility with Migen AsyncResetSynchronizer	David Shah	2019-02-25	2	-0/+20
\| *	ecp5: Add DDRDLLA	David Shah	2019-02-19	1	-0/+9
\| *	ecp5: Add DELAYF/DELAYG blackboxes	David Shah	2019-02-19	1	-0/+18
\| *	ecp5: Add ECLKSYNCB blackbox	David Shah	2019-02-13	1	-1/+7
\| *	ecp5: Full set of IO-related blackboxes	David Shah	2019-02-12	1	-0/+102
\| *	ecp5: Support for flipflop initialisation	David Shah	2019-01-22	3	-4/+199
\| *	ecp5: Add LSRMODE to flipflops for PRLD support	David Shah	2019-01-21	1	-7/+16
\| *	ecp5: More blackboxes	David Shah	2019-01-21	1	-0/+17
\| *	ecp5: Increase threshold for ALU mapping	David Shah	2019-01-21	1	-1/+1
* \|	techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module	Larry Doolittle	2019-02-26	1	-22/+22
* \|	Clean up some whitepsace outliers	Larry Doolittle	2019-02-26	1	-2/+2
* \|	Merge pull request #740 from daveshah1/improve_dress	Clifford Wolf	2019-02-22	2	-3/+3
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\| * \|	ecp5: Use abc -dress	David Shah	2019-02-06	1	-2/+2
\| * \|	ice40: Use abc -dress in synth_ice40	David Shah	2019-02-06	1	-1/+1
* \| \|	Bugfix in ice40_dsp	Clifford Wolf	2019-02-21	2	-20/+33
* \| \|	Add ice40 test_dsp_map test case generator	Clifford Wolf	2019-02-20	2	-0/+99
* \| \|	Add "synth_ice40 -dsp"	Clifford Wolf	2019-02-20	1	-3/+27
* \| \|	Improve iCE40 SB_MAC16 model	Clifford Wolf	2019-02-20	5	-121/+179
* \| \|	Add first draft of functional SB_MAC16 model	Clifford Wolf	2019-02-19	4	-53/+467
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* /	Fixed Anlogic simulation model	Miodrag Milanovic	2019-01-25	1	-1/+1
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*	Add SF2 IO buffer insertion	Clifford Wolf	2019-01-17	4	-1/+168
*	Add "synth_sf2 -vlog", fix "synth_sf2 -edif"	Clifford Wolf	2019-01-17	1	-2/+17
*	Merge pull request #777 from mmicko/achronix_cell_sim_fix	Clifford Wolf	2019-01-04	1	-1/+1
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\| *	Fix cells_sim.v for Achronix FPGA	Miodrag Milanovic	2019-01-04	1	-1/+1