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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-20 16:42:27 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-20 16:42:27 +0100 |
| commit | 218e9051bbdbbd00620a21e6918e6a4b9bc07867 (patch) | |
| tree | ec0a12115b1391c248a6878b46b1fca6656c9c7e /techlibs | |
| parent | 246391200e3e0d47ee571d4d77dd0744dba0e164 (diff) | |
| download | yosys-218e9051bbdbbd00620a21e6918e6a4b9bc07867.tar.gz yosys-218e9051bbdbbd00620a21e6918e6a4b9bc07867.tar.bz2 yosys-218e9051bbdbbd00620a21e6918e6a4b9bc07867.zip | |
Add "synth_ice40 -dsp"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 30 |
1 files changed, 27 insertions, 3 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index f900453e8..d6d047fe7 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -79,6 +79,9 @@ struct SynthIce40Pass : public ScriptPass log(" -nobram\n"); log(" do not use SB_RAM40_4K* cells in output netlist\n"); log("\n"); + log(" -dsp\n"); + log(" use iCE40 UltraPlus DSP cells for large arithmetic\n"); + log("\n"); log(" -noabc\n"); log(" use built-in Yosys LUT techmapping instead of abc\n"); log("\n"); @@ -96,7 +99,7 @@ struct SynthIce40Pass : public ScriptPass } string top_opt, blif_file, edif_file, json_file; - bool nocarry, nodffe, nobram, flatten, retime, relut, noabc, abc2, vpr; + bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr; int min_ce_use; void clear_flags() YS_OVERRIDE @@ -109,6 +112,7 @@ struct SynthIce40Pass : public ScriptPass nodffe = false; min_ce_use = -1; nobram = false; + dsp = false; flatten = true; retime = false; relut = false; @@ -181,6 +185,10 @@ struct SynthIce40Pass : public ScriptPass nobram = true; continue; } + if (args[argidx] == "-dsp") { + dsp = true; + continue; + } if (args[argidx] == "-noabc") { noabc = true; continue; @@ -214,11 +222,11 @@ struct SynthIce40Pass : public ScriptPass { run("read_verilog -lib +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); + run("proc"); } if (flatten && check_label("flatten", "(unless -noflatten)")) { - run("proc"); run("flatten"); run("tribuf -logic"); run("deminout"); @@ -226,7 +234,23 @@ struct SynthIce40Pass : public ScriptPass if (check_label("coarse")) { - run("synth -lut 4 -run coarse"); + run("opt_expr"); + run("opt_clean"); + run("check"); + run("opt"); + run("wreduce"); + run("share"); + run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); + run("opt_expr"); + run("opt_clean"); + if (help_mode || dsp) + run("ice40_dsp", "(if -dsp)"); + run("alumacc"); + run("opt"); + run("fsm"); + run("opt -fast"); + run("memory -nomap"); + run("opt_clean"); } if (!nobram && check_label("bram", "(skip if -nobram)")) |