Improvements in sf2 cells_sim.v

Signed-off-by: Clifford Wolf <clifford@clifford.at>

2 files changed, 251 insertions, 30 deletions

diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
index b49101616..f3f7695cf 100644
--- a/techlibs/sf2/cells_sim.v
+++ b/techlibs/sf2/cells_sim.v
@@ -1,3 +1,111 @@
+module CFG1 (
+	output Y,
+	input A
+);
+	parameter [1:0] INIT = 2'h0;
+	assign Y = INIT >> A;
+endmodule
+
+module CFG2 (
+	output Y,
+	input A,
+	input B
+);
+	parameter [3:0] INIT = 4'h0;
+	assign Y = INIT >> {B, A};
+endmodule
+
+module CFG3 (
+	output Y,
+	input A,
+	input B,
+	input C
+);
+	parameter [7:0] INIT = 8'h0;
+	assign Y = INIT >> {C, B, A};
+endmodule
+
+module CFG4 (
+	output Y,
+	input A,
+	input B,
+	input C,
+	input D
+);
+	parameter [15:0] INIT = 16'h0;
+	assign Y = INIT >> {D, C, B, A};
+endmodule
+
+module ADD2 (
+	input A, B,
+	output Y
+);
+	assign Y = A & B;
+endmodule
+
+module ADD3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = A & B & C;
+endmodule
+
+module ADD4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = A & B & C & D;
+endmodule
+
+module BUFF (
+	input A,
+	output Y
+);
+	assign Y = A;
+endmodule
+
+module BUFD (
+	input A,
+	output Y
+);
+	assign Y = A;
+endmodule
+
+module CLKINT (
+	input A,
+	output Y
+);
+	assign Y = A;
+endmodule
+
+module CLKINT_PRESERVE (
+	input A,
+	output Y
+);
+	assign Y = A;
+endmodule
+
+module GCLKINT (
+	input A, EN,
+	output Y
+);
+	assign Y = A & EN;
+endmodule
+
+module RCLKINT (
+	input A,
+	output Y
+);
+	assign Y = A;
+endmodule
+
+module RGCLKINT (
+	input A, EN,
+	output Y
+);
+	assign Y = A & EN;
+endmodule
+
 module SLE (
 	output Q,
 	input ADn,
@@ -36,51 +144,151 @@ module SLE (
 	assign Q = LAT ? q_latch : q_ff;
 endmodule
 
-module CFG1 (
-	output Y,
-	input A
+// module AR1
+// module FCEND_BUFF
+// module FCINIT_BUFF
+// module FLASH_FREEZE
+// module OSCILLATOR
+// module SYSRESET
+// module SYSCTRL_RESET_STATUS
+// module LIVE_PROBE_FB
+// module GCLKBUF
+// module GCLKBUF_DIFF
+// module GCLKBIBUF
+// module DFN1
+// module DFN1C0
+// module DFN1E1
+// module DFN1E1C0
+// module DFN1E1P0
+// module DFN1P0
+// module DLN1
+// module DLN1C0
+// module DLN1P0
+
+module INV (
+	input A,
+	output Y
 );
-	parameter [1:0] INIT = 2'h0;
-	assign Y = INIT >> A;
+	assign Y = !A;
 endmodule
 
-module CFG2 (
-	output Y,
+module INVD (
 	input A,
-	input B
+	output Y
 );
-	parameter [3:0] INIT = 4'h0;
-	assign Y = INIT >> {B, A};
+	assign Y = !A;
 endmodule
 
-module CFG3 (
-	output Y,
-	input A,
-	input B,
-	input C
+module MX2 (
+	input A, B, S,
+	output Y
 );
-	parameter [7:0] INIT = 8'h0;
-	assign Y = INIT >> {C, B, A};
+	assign Y = S ? B : A;
 endmodule
 
-module CFG4 (
-	output Y,
-	input A,
-	input B,
-	input C,
-	input D
+module MX4 (
+	input D0, D1, D2, D3, S0, S1,
+	output Y
 );
-	parameter [15:0] INIT = 16'h0;
-	assign Y = INIT >> {D, C, B, A};
+	assign Y = S1 ? (S0 ? D3 : D2) : (S0 ? D1 : D0);
 endmodule
 
-module CLKINT (
-	input A,
+module NAND2 (
+	input A, B,
 	output Y
 );
-	assign Y = A;
+	assign Y = !(A & B);
+endmodule
+
+module NAND3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = !(A & B & C);
 endmodule
 
+module NAND4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = !(A & B & C & D);
+endmodule
+
+module NOR2 (
+	input A, B,
+	output Y
+);
+	assign Y = !(A | B);
+endmodule
+
+module NOR3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = !(A | B | C);
+endmodule
+
+module NOR4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = !(A | B | C | D);
+endmodule
+
+module OR2 (
+	input A, B,
+	output Y
+);
+	assign Y = A | B;
+endmodule
+
+module OR3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = A | B | C;
+endmodule
+
+module OR4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = A | B | C | D;
+endmodule
+
+module XOR2 (
+	input A, B,
+	output Y
+);
+	assign Y = A ^ B;
+endmodule
+
+module XOR3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = A ^ B ^ C;
+endmodule
+
+module XOR4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = A ^ B ^ C ^ D;
+endmodule
+
+module XOR8 (
+	input A, B, C, D, E, F, G, H,
+	output Y
+);
+	assign Y = A ^ B ^ C ^ D ^ E ^ F ^ G ^ H;
+endmodule
+
+// module UJTAG
+// module BIBUF
+// module BIBUF_DIFF
+// module CLKBIBUF
+
 module CLKBUF (
 	input PAD,
 	output Y
@@ -88,6 +296,8 @@ module CLKBUF (
 	assign Y = PAD;
 endmodule
 
+// module CLKBUF_DIFF
+
 module INBUF (
 	input PAD,
 	output Y
@@ -95,9 +305,20 @@ module INBUF (
 	assign Y = PAD;
 endmodule
 
+// module INBUF_DIFF
+
 module OUTBUF (
 	input D,
 	output PAD
 );
 	assign PAD = D;
 endmodule
+
+// module OUTBUF_DIFF
+// module TRIBUFF
+// module TRIBUFF_DIFF
+// module DDR_IN
+// module DDR_OUT
+// module RAM1K18
+// module RAM64x18
+// module MACC
diff --git a/techlibs/sf2/sf2_iobs.cc b/techlibs/sf2/sf2_iobs.cc
index dea8e353b..3d43332e2 100644
--- a/techlibs/sf2/sf2_iobs.cc
+++ b/techlibs/sf2/sf2_iobs.cc
@@ -38,8 +38,8 @@ static void handle_iobufs(Module *module, bool clkbuf_mode)
 			for (auto bit : sigmap(cell->getPort("\\CLK")))
 				clk_bits.insert(bit);
 		}
-		if (cell->type.in("\\INBUF", "\\OUTBUF", "\\TRIBUF", "\\BIBUF", "\\CLKBUF", "\\CLKBIBUF",
-				"\\INBUF_DIFF", "\\OUTBUF_DIFF", "\\BIBUFF_DIFF", "\\TRIBUF_DIFF", "\\CLKBUF_DIFF",
+		if (cell->type.in("\\INBUF", "\\OUTBUF", "\\TRIBUFF", "\\BIBUF", "\\CLKBUF", "\\CLKBIBUF",
+				"\\INBUF_DIFF", "\\OUTBUF_DIFF", "\\BIBUFF_DIFF", "\\TRIBUFF_DIFF", "\\CLKBUF_DIFF",
 				"\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF")) {
 			for (auto bit : sigmap(cell->getPort("\\PAD")))
 				handled_io_bits.insert(bit);