diff options
author | Keith Rothman <537074+litghost@users.noreply.github.com> | 2019-03-01 14:41:21 -0800 |
---|---|---|
committer | Keith Rothman <537074+litghost@users.noreply.github.com> | 2019-03-01 14:41:21 -0800 |
commit | 3e16f75bc6f490cada2b9c4e9b4962a66b1e8008 (patch) | |
tree | f372d1558342d6598f132263c4d1471619d493cb /techlibs | |
parent | 5ebeca12eb0bf9317acec3d619021ab337d445ba (diff) | |
download | yosys-3e16f75bc6f490cada2b9c4e9b4962a66b1e8008.tar.gz yosys-3e16f75bc6f490cada2b9c4e9b4962a66b1e8008.tar.bz2 yosys-3e16f75bc6f490cada2b9c4e9b4962a66b1e8008.zip |
Revert FF models to include IS_x_INVERTED parameters.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/xilinx/cells_sim.v | 40 |
1 files changed, 34 insertions, 6 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 787b37cc8..ff5ff0726 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -147,26 +147,54 @@ endmodule module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_R_INVERTED = 1'b0; initial Q <= INIT; - always @(posedge C) if (R) Q <= 1'b0; else if(CE) Q <= D; + generate case (|IS_C_INVERTED) + 1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + endcase endgenerate endmodule module FDSE (output reg Q, input C, CE, D, S); - parameter [0:0] INIT = 1'b1; + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_S_INVERTED = 1'b0; initial Q <= INIT; - always @(posedge C) if (S) Q <= 1'b1; else if(CE) Q <= D; + generate case (|IS_C_INVERTED) + 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + endcase endgenerate endmodule module FDCE (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; initial Q <= INIT; - always @(posedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; + generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) + 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + endcase endgenerate endmodule module FDPE (output reg Q, input C, CE, D, PRE); - parameter [0:0] INIT = 1'b1; + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; initial Q <= INIT; - always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; + generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) + 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + endcase endgenerate endmodule module FDRE_1 (output reg Q, input C, CE, D, R); |