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* Trim Y_WIDTHEddie Hung2019-08-011-5/+3
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* Add DSP_SIGNEDONLY backEddie Hung2019-08-011-0/+16
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* DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTHEddie Hung2019-08-012-5/+12
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* Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
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* Revert "Do not do sign extension in techmap; let packer do it"Eddie Hung2019-08-011-5/+14
| | | | This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd.
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-016-18/+24
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| * RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
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| * Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-254-5/+11
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| | * intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-234-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.
| * | Merge pull request #1218 from ZirconiumX/synth_intel_iopadsClifford Wolf2019-07-251-8/+8
| |\ \ | | | | | | | | intel: Make -noiopads the default
| | * | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
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| * | | Merge pull request #1224 from YosysHQ/xilinx_fix_ffEddie Hung2019-07-251-2/+2
| |\ \ \ | | |/ / | |/| | xilinx: Fix missing cell name underscore in cells_map.v
| | * | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Fix B_WIDTH > DSP_B_MAXWIDTH caseEddie Hung2019-08-011-32/+14
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* | | | Do not compute sign bit if result is zeroEddie Hung2019-07-311-1/+2
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* | | | For signed multipliers, compute sign bit separately...Eddie Hung2019-07-311-23/+42
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* | | | Fix spacingEddie Hung2019-07-261-3/+3
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* | | | Add copyright header, comment on cascadeEddie Hung2019-07-241-4/+34
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* | | | Typo for Y_WIDTHEddie Hung2019-07-231-1/+1
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* | | | Remove debugEddie Hung2019-07-221-1/+0
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* | | | Rename according to vendor doc TN1295Eddie Hung2019-07-221-0/+1
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* | | | opt and wreduce necessary for -dspEddie Hung2019-07-221-2/+4
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* | | | Use minimum sized width wiresEddie Hung2019-07-221-7/+13
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* | | | Indirection via $__soft_mulEddie Hung2019-07-192-9/+10
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* | | | Do not do sign extension in techmap; let packer do itEddie Hung2019-07-191-14/+5
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* | | | Do not $mul -> $__mul if A and B are less than maxwidthEddie Hung2019-07-191-1/+3
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* | | | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this thresholdEddie Hung2019-07-191-1/+1
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* | | | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 tooEddie Hung2019-07-191-28/+68
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* | | | Merge branch 'xc7dsp' into ice40dspEddie Hung2019-07-191-1/+1
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| * | | | Fix typo in BEddie Hung2019-07-191-1/+1
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| * | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1815-84/+164
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* | | | | Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dspEddie Hung2019-07-193-7/+239
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| * | | | ice40: Fix test_dsp_model.shDavid Shah2019-07-191-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | ice40/cells_sim.v: Fix sign of J and K partial productsDavid Shah2019-07-191-5/+7
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 modeDavid Shah2019-07-191-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | Add tests for all combinations of A and B signedness for comb mulEddie Hung2019-07-192-1/+229
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| * | | | Don't copy ref if exists alreadyEddie Hung2019-07-191-1/+3
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* | | | Use sign_headroom insteadEddie Hung2019-07-191-4/+4
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* | | | Fix SB_MAC sim model -- do not sign extend internal products?Eddie Hung2019-07-181-2/+2
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* | | | Add paramsEddie Hung2019-07-181-0/+6
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* | | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-181-33/+18
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| * | | Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
| |\ \ \ | | | | | | | | | | Assorted synth_intel cleanups from @bwidawsk
| | * | | synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
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| | * | | synth_intel: s/not family/no family/Dan Ravensloft2019-07-181-2/+2
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| | * | | intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cyclonev has been a "supported" family since the initial commit. The old commit message suggested to use a10gx which is incorrect. Aside from the obvious lack of functional change due to this just being a help message, users who were previously using "a10gx" for "cyclonev" will also have no functional change by using "cyclonev" instead. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| | * | | intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-181-28/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| | * | | intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The help and code default to MAX10 for the family, however the couple of if ladders defaulted to cycloneive. Fix this inconsistency and the next patch will clean it up. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| | * | | intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | | | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
| |/ / / | | | | | | | | | | | | Also fix a typo in the help message.
* | | | Do not define `DSP_SIGNEDONLY macro if no existsEddie Hung2019-07-181-4/+3
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