| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Do not overwrite LUT param | Eddie Hung | 2019-08-28 | 1 | -1/+0 |
| * | Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival | Eddie Hung | 2019-08-28 | 2 | -1/+48 |
| |\ | |||||
| | * | Trailing comma | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
| | * | Adapt to $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-28 | 1 | -3/+5 |
| | * | Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with" | Eddie Hung | 2019-08-28 | 1 | -0/+45 |
| * | | Add arrival times for HX devices | Eddie Hung | 2019-08-28 | 1 | -21/+114 |
| * | | Specify ice40 family to cells_sim.v using define | Eddie Hung | 2019-08-28 | 1 | -1/+8 |
| * | | Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival | Eddie Hung | 2019-08-28 | 5 | -68/+20 |
| |\| | |||||
| | * | Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with | Eddie Hung | 2019-08-28 | 1 | -45/+0 |
| | * | Update box size and timings | Eddie Hung | 2019-08-28 | 3 | -12/+12 |
| | * | Update to new $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-28 | 1 | -11/+8 |
| * | | Merge branch 'eddie/xilinx_srl' into xaig_arrival | Eddie Hung | 2019-08-28 | 1 | -15/+22 |
| |\ \ | |||||
| | * \ | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-28 | 13 | -248/+835 |
| | |\ \ | |||||
| | * \ \ | Merge branch 'master' into eddie/xilinx_srl | Eddie Hung | 2019-08-26 | 1 | -0/+8 |
| | |\ \ \ | |||||
| | * | | | | xilinx_srl now copes with word-level flops $dff{,e} | Eddie Hung | 2019-08-23 | 1 | -8/+3 |
| | * | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-23 | 3 | -15/+30 |
| | |\ \ \ \ | |||||
| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 14 | -92/+961 |
| | |\ \ \ \ \ | |||||
| | * | | | | | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 1 | -4/+3 |
| | * | | | | | | abc9 to perform new 'map_ffs' before 'map_luts' | Eddie Hung | 2019-08-21 | 1 | -3/+18 |
| | * | | | | | | Add init support | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
| * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-28 | 13 | -249/+865 |
| |\ \ \ \ \ \ \ | | |_|_|_|_|/ | |/| | | | | | |||||
| | * | | | | | | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor | Eddie Hung | 2019-08-28 | 1 | -3/+8 |
| | | |_|_|_|/ | |/| | | | | |||||
| | * | | | | | Merge pull request #1332 from YosysHQ/dave/ecp5gsr | David Shah | 2019-08-28 | 6 | -54/+212 |
| | |\ \ \ \ \ | |||||
| | | * | | | | | ecp5: Add GSR support | David Shah | 2019-08-27 | 6 | -54/+212 |
| | | | |_|_|/ | | |/| | | | |||||
| | * | | | | | xilinx: Add SRLC16E primitive. | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+21 |
| | * | | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 1 | -0/+8 |
| | |\| | | | | |||||
| | | * | | | | Add undocumented feature | Eddie Hung | 2019-08-23 | 1 | -0/+8 |
| | | | |_|/ | | |/| | | |||||
| | * | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
| | |\| | | | |||||
| | * | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 3 | -18/+36 |
| | |\ \ \ \ | |||||
| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 29 | -299/+1059 |
| | |\ \ \ \ \ | | | |_|_|/ | | |/| | | | |||||
| | * | | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 6 | -283/+537 |
| | * | | | | | minor review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -1/+1 |
| | * | | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -18/+27 |
| | * | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 6 | -71/+220 |
| * | | | | | | Fix spacing | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
| * | | | | | | Remove unused model | Eddie Hung | 2019-08-23 | 1 | -13/+0 |
| * | | | | | | Put attributes above port | Eddie Hung | 2019-08-23 | 2 | -27/+62 |
| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-23 | 17 | -102/+981 |
| |\ \ \ \ \ \ | | |_|_|/ / | |/| | | | | |||||
| | * | | | | | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 |
| | | |_|/ / | |/| | | | |||||
| | * | | | | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 3 | -14/+28 |
| | | |/ / | |/| | | |||||
| | * | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | * | | | Merge pull request #1289 from mmicko/anlogic_fixes | Clifford Wolf | 2019-08-22 | 5 | -91/+162 |
| | |\ \ \ | |||||
| | | * \ \ | Merge remote-tracking branch 'upstream/master' into anlogic_fixes | Miodrag Milanovic | 2019-08-18 | 7 | -165/+37 |
| | | |\ \ \ | |||||
| | | * | | | | Proper arith for Anlogic and use standard pass | Miodrag Milanovic | 2019-08-12 | 5 | -91/+162 |
| | | | |/ / | | |/| | | |||||
| | * | | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | * | | | | Merge pull request #1281 from mmicko/efinix | Clifford Wolf | 2019-08-22 | 9 | -0/+798 |
| | |\ \ \ \ | | |_|_|/ | |/| | | | |||||
| | | * | | | Fix formating | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 |
| | | * | | | one bit enable signal | Miodrag Milanovic | 2019-08-11 | 1 | -1/+1 |
| | | * | | | fix mixing signals on FF mapping | Miodrag Milanovic | 2019-08-11 | 1 | -4/+4 |
| | | * | | | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 3 | -91/+1 |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |