index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
techlibs
Commit message (
Expand
)
Author
Age
Files
Lines
*
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
Eddie Hung
2019-09-25
1
-1
/
+1
*
Add (* techmap_autopurge *) to abc_unmap.v too
Eddie Hung
2019-09-23
1
-11
/
+11
*
Add techmap_autopurge to outputs in abc_map.v too
Eddie Hung
2019-09-23
1
-11
/
+11
*
Revert "Add a xilinx_finalise pass"
Eddie Hung
2019-09-23
3
-87
/
+0
*
Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"
Eddie Hung
2019-09-23
1
-38
/
+38
*
Revert "Vivado does not like zero width port connections"
Eddie Hung
2019-09-23
1
-2
/
+2
*
Vivado does not like zero width port connections
Eddie Hung
2019-09-23
1
-2
/
+2
*
Remove (* techmap_autopurge *) from abc_unmap.v since no effect
Eddie Hung
2019-09-23
1
-38
/
+38
*
Add a xilinx_finalise pass
Eddie Hung
2019-09-23
3
-0
/
+87
*
Grammar
Eddie Hung
2019-09-20
1
-1
/
+1
*
Fix signedness bug
Eddie Hung
2019-09-20
1
-2
/
+2
*
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
Eddie Hung
2019-09-20
2
-3
/
+2
*
Revert "Move mul2dsp before wreduce"
Eddie Hung
2019-09-20
1
-4
/
+5
*
Move mul2dsp before wreduce
Eddie Hung
2019-09-20
1
-5
/
+4
*
Tidy up, fix undriven
Eddie Hung
2019-09-19
1
-32
/
+34
*
$__ABC_REG to have WIDTH parameter
Eddie Hung
2019-09-19
2
-17
/
+18
*
Fix DSP48E1 timing by breaking P path if MREG or PREG
Eddie Hung
2019-09-19
4
-349
/
+363
*
Revert "Different approach to timing"
Eddie Hung
2019-09-19
4
-195
/
+405
*
Different approach to timing
Eddie Hung
2019-09-19
4
-405
/
+195
*
Suppress $anyseq warnings
Eddie Hung
2019-09-19
1
-15
/
+32
*
Use (* techmap_autopurge *) to suppress techmap warnings
Eddie Hung
2019-09-19
2
-94
/
+99
*
D is 25 bits not 24 bits wide
Eddie Hung
2019-09-19
1
-1
/
+1
*
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
Eddie Hung
2019-09-19
8
-90
/
+502
|
\
|
*
Use extractinv for synth_xilinx -ise
Marcin Kościelnicki
2019-09-19
8
-90
/
+502
*
|
synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2
Eddie Hung
2019-09-19
1
-1
/
+4
*
|
Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2
Eddie Hung
2019-09-19
1
-1
/
+3
*
|
Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-09-18
9
-948
/
+19414
|
\
|
|
*
Merge pull request #1379 from mmicko/sim_models
Eddie Hung
2019-09-18
2
-7
/
+162
|
|
\
|
|
*
make note that it is for latch mode
Miodrag Milanovic
2019-09-18
1
-0
/
+1
|
|
*
better lut handling
Miodrag Milanovic
2019-09-18
1
-4
/
+14
|
|
*
better handling of lut and begin/end add
Miodrag Milanovic
2019-09-18
1
-4
/
+10
|
|
*
Added simulation models for Efinix and Anlogic
Miodrag Milanovic
2019-09-15
2
-3
/
+141
|
*
|
xilinx: Make blackbox library family-dependent.
Marcin Kościelnicki
2019-09-15
7
-1024
/
+19252
|
|
/
*
|
Fix copy-paste
Eddie Hung
2019-09-18
1
-2
/
+2
*
|
Mis-spell
Eddie Hung
2019-09-18
1
-10
/
+25
*
|
Add pattern detection support for DSP48E1 model, check against vendor
Eddie Hung
2019-09-18
3
-8
/
+102
*
|
Add `undef DSP48E1_INST
Eddie Hung
2019-09-13
1
-4
/
+5
*
|
Fix D -> P{,COUT} delay
Eddie Hung
2019-09-13
1
-43
/
+43
*
|
Add no MULT no DPORT config
Eddie Hung
2019-09-13
4
-226
/
+471
*
|
Add support for MULT and DPORT
Eddie Hung
2019-09-13
4
-10
/
+588
*
|
Refine diagram
Eddie Hung
2019-09-13
1
-12
/
+14
*
|
Add an ASCII drawing
Eddie Hung
2019-09-12
1
-3
/
+22
*
|
Finish explanation
Eddie Hung
2019-09-12
2
-5
/
+20
*
|
Rename to techmap_guard
Eddie Hung
2019-09-12
1
-2
/
+3
*
|
Initial DSP48E1 box support
Eddie Hung
2019-09-12
4
-0
/
+867
*
|
Set more ports explicitly
Eddie Hung
2019-09-12
1
-1
/
+2
*
|
Missing space
Eddie Hung
2019-09-11
1
-0
/
+1
*
|
Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-09-11
5
-53
/
+219
|
\
|
|
*
synth_xilinx: Support init values on Spartan 6 flip-flops properly.
Marcin Kościelnicki
2019-09-07
5
-53
/
+219
*
|
Move "(skip if -nodsp)" message to label
Eddie Hung
2019-09-10
1
-4
/
+4
[next]