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* Oops. Actually use __NAME__ in ABC_DSP48E1 macroEddie Hung2019-09-251-1/+1
* Add (* techmap_autopurge *) to abc_unmap.v tooEddie Hung2019-09-231-11/+11
* Add techmap_autopurge to outputs in abc_map.v tooEddie Hung2019-09-231-11/+11
* Revert "Add a xilinx_finalise pass"Eddie Hung2019-09-233-87/+0
* Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"Eddie Hung2019-09-231-38/+38
* Revert "Vivado does not like zero width port connections"Eddie Hung2019-09-231-2/+2
* Vivado does not like zero width port connectionsEddie Hung2019-09-231-2/+2
* Remove (* techmap_autopurge *) from abc_unmap.v since no effectEddie Hung2019-09-231-38/+38
* Add a xilinx_finalise passEddie Hung2019-09-233-0/+87
* GrammarEddie Hung2019-09-201-1/+1
* Fix signedness bugEddie Hung2019-09-201-2/+2
* Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-202-3/+2
* Revert "Move mul2dsp before wreduce"Eddie Hung2019-09-201-4/+5
* Move mul2dsp before wreduceEddie Hung2019-09-201-5/+4
* Tidy up, fix undrivenEddie Hung2019-09-191-32/+34
* $__ABC_REG to have WIDTH parameterEddie Hung2019-09-192-17/+18
* Fix DSP48E1 timing by breaking P path if MREG or PREGEddie Hung2019-09-194-349/+363
* Revert "Different approach to timing"Eddie Hung2019-09-194-195/+405
* Different approach to timingEddie Hung2019-09-194-405/+195
* Suppress $anyseq warningsEddie Hung2019-09-191-15/+32
* Use (* techmap_autopurge *) to suppress techmap warningsEddie Hung2019-09-192-94/+99
* D is 25 bits not 24 bits wideEddie Hung2019-09-191-1/+1
* Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-198-90/+502
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| * Use extractinv for synth_xilinx -iseMarcin Kościelnicki2019-09-198-90/+502
* | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2Eddie Hung2019-09-191-1/+4
* | Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2Eddie Hung2019-09-191-1/+3
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-189-948/+19414
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| * Merge pull request #1379 from mmicko/sim_modelsEddie Hung2019-09-182-7/+162
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| | * make note that it is for latch modeMiodrag Milanovic2019-09-181-0/+1
| | * better lut handlingMiodrag Milanovic2019-09-181-4/+14
| | * better handling of lut and begin/end addMiodrag Milanovic2019-09-181-4/+10
| | * Added simulation models for Efinix and AnlogicMiodrag Milanovic2019-09-152-3/+141
| * | xilinx: Make blackbox library family-dependent.Marcin Kościelnicki2019-09-157-1024/+19252
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* | Fix copy-pasteEddie Hung2019-09-181-2/+2
* | Mis-spellEddie Hung2019-09-181-10/+25
* | Add pattern detection support for DSP48E1 model, check against vendorEddie Hung2019-09-183-8/+102
* | Add `undef DSP48E1_INSTEddie Hung2019-09-131-4/+5
* | Fix D -> P{,COUT} delayEddie Hung2019-09-131-43/+43
* | Add no MULT no DPORT configEddie Hung2019-09-134-226/+471
* | Add support for MULT and DPORTEddie Hung2019-09-134-10/+588
* | Refine diagramEddie Hung2019-09-131-12/+14
* | Add an ASCII drawingEddie Hung2019-09-121-3/+22
* | Finish explanationEddie Hung2019-09-122-5/+20
* | Rename to techmap_guardEddie Hung2019-09-121-2/+3
* | Initial DSP48E1 box supportEddie Hung2019-09-124-0/+867
* | Set more ports explicitlyEddie Hung2019-09-121-1/+2
* | Missing spaceEddie Hung2019-09-111-0/+1
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-115-53/+219
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| * synth_xilinx: Support init values on Spartan 6 flip-flops properly.Marcin Kościelnicki2019-09-075-53/+219
* | Move "(skip if -nodsp)" message to labelEddie Hung2019-09-101-4/+4
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