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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 14:58:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 14:58:06 -0700 |
| commit | 95db2489bdb515a2e9d3a995574adc8c1071d3c0 (patch) | |
| tree | a5b34f8630a5a940a37f278ddd20b7816394d182 /techlibs | |
| parent | 3b9b0fcd0630133092b23a18453eb420534b2369 (diff) | |
| download | yosys-95db2489bdb515a2e9d3a995574adc8c1071d3c0.tar.gz yosys-95db2489bdb515a2e9d3a995574adc8c1071d3c0.tar.bz2 yosys-95db2489bdb515a2e9d3a995574adc8c1071d3c0.zip | |
synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 2ac254a1f..b55c40764 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -342,7 +342,10 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_dsp"), "(skip if '-nodsp')") { if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only - run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); + run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " + "-D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers + "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller + "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); run("xilinx_dsp"); run("chtype -set $mul t:$__soft_mul"); } |