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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 21:56:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 21:56:28 -0700 |
| commit | 11ac37733d436d5c0217fa6da029d620ec3da1b3 (patch) | |
| tree | 9f0fa595c0a2ec5aba4604ae3cb248537860e586 /techlibs | |
| parent | 27167848f4c5709c6ca3cb0897bac91c4a2a7cbe (diff) | |
| download | yosys-11ac37733d436d5c0217fa6da029d620ec3da1b3.tar.gz yosys-11ac37733d436d5c0217fa6da029d620ec3da1b3.tar.bz2 yosys-11ac37733d436d5c0217fa6da029d620ec3da1b3.zip | |
Add techmap_autopurge to outputs in abc_map.v too
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_map.v | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 9d78725df..e4976092c 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -123,17 +123,17 @@ module SRLC32E ( endmodule module DSP48E1 ( - output [29:0] ACOUT, - output [17:0] BCOUT, - output reg CARRYCASCOUT, - output reg [3:0] CARRYOUT, - output reg MULTSIGNOUT, - output OVERFLOW, - output reg signed [47:0] P, - output PATTERNBDETECT, - output PATTERNDETECT, - output [47:0] PCOUT, - output UNDERFLOW, + (* techmap_autopurge *) output [29:0] ACOUT, + (* techmap_autopurge *) output [17:0] BCOUT, + (* techmap_autopurge *) output reg CARRYCASCOUT, + (* techmap_autopurge *) output reg [3:0] CARRYOUT, + (* techmap_autopurge *) output reg MULTSIGNOUT, + (* techmap_autopurge *) output OVERFLOW, + (* techmap_autopurge *) output reg signed [47:0] P, + (* techmap_autopurge *) output PATTERNBDETECT, + (* techmap_autopurge *) output PATTERNDETECT, + (* techmap_autopurge *) output [47:0] PCOUT, + (* techmap_autopurge *) output UNDERFLOW, (* techmap_autopurge *) input signed [29:0] A, (* techmap_autopurge *) input [29:0] ACIN, (* techmap_autopurge *) input [3:0] ALUMODE, |