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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 15:55:49 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 15:55:49 -0700 |
| commit | c15a35db8487a31592046bfe8422740e196407d1 (patch) | |
| tree | 41d77d5aaa9acaf365e25ecece42d7104358e685 /techlibs | |
| parent | b88f0f6450a4d9db4c926a4636968f12d763096b (diff) | |
| download | yosys-c15a35db8487a31592046bfe8422740e196407d1.tar.gz yosys-c15a35db8487a31592046bfe8422740e196407d1.tar.bz2 yosys-c15a35db8487a31592046bfe8422740e196407d1.zip | |
D is 25 bits not 24 bits wide
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/dsp_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 8901b215b..a4256eb92 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -32,7 +32,7 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .A({{5{A[24]}}, A}), .B(B), .C(48'b0), - .D(24'b0), + .D(25'b0), .P(P_48), .INMODE(5'b00000), |