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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-09-18 17:45:19 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-09-18 17:45:19 +0200 |
| commit | b0ca6de472dcbba50776ac21cf450eb89ee33447 (patch) | |
| tree | 02e34bac799cac4d1ad82cbbea47303611c215bb /techlibs | |
| parent | 8badd4d812e30c79a3fe75694ef8d8289f08abc7 (diff) | |
| download | yosys-b0ca6de472dcbba50776ac21cf450eb89ee33447.tar.gz yosys-b0ca6de472dcbba50776ac21cf450eb89ee33447.tar.bz2 yosys-b0ca6de472dcbba50776ac21cf450eb89ee33447.zip | |
better lut handling
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/anlogic/cells_sim.v | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v index 652de3b26..cea9f8c11 100644 --- a/techlibs/anlogic/cells_sim.v +++ b/techlibs/anlogic/cells_sim.v @@ -81,7 +81,8 @@ module AL_MAP_LUT1 ( ); parameter [1:0] INIT = 2'h0; parameter EQN = "(A)"; - assign o = INIT >> a; + + assign o = a ? INIT[1] : INIT[0]; endmodule module AL_MAP_LUT2 ( @@ -91,7 +92,9 @@ module AL_MAP_LUT2 ( ); parameter [3:0] INIT = 4'h0; parameter EQN = "(A)"; - assign o = INIT >> {b, a}; + + wire [1:0] s1 = b ? INIT[ 3:2] : INIT[1:0]; + assign o = a ? s1[1] : s1[0]; endmodule module AL_MAP_LUT3 ( @@ -102,7 +105,10 @@ module AL_MAP_LUT3 ( ); parameter [7:0] INIT = 8'h0; parameter EQN = "(A)"; - assign o = INIT >> {c, b, a}; + + wire [3:0] s2 = c ? INIT[ 7:4] : INIT[3:0]; + wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0]; + assign o = a ? s1[1] : s1[0]; endmodule module AL_MAP_LUT4 ( @@ -114,7 +120,11 @@ module AL_MAP_LUT4 ( ); parameter [15:0] INIT = 16'h0; parameter EQN = "(A)"; - assign o = INIT >> {d, c, b, a}; + + wire [7:0] s3 = d ? INIT[15:8] : INIT[7:0]; + wire [3:0] s2 = c ? s3[ 7:4] : s3[3:0]; + wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0]; + assign o = a ? s1[1] : s1[0]; endmodule module AL_MAP_LUT5 ( |