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Author
Age
Files
Lines
*
Typo
Eddie Hung
2019-05-28
1
-1
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+1
*
Make MUXF{7,8} and CARRY4 whitebox
Eddie Hung
2019-05-27
1
-3
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+3
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Re-enable lib_whitebox
Eddie Hung
2019-05-27
1
-5
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+5
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Blackboxes
Eddie Hung
2019-05-26
2
-10
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+10
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Muck about with LUT delays some more
Eddie Hung
2019-05-26
1
-5
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+5
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Try new LUT delays
Eddie Hung
2019-05-24
1
-8
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+11
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Transpose CARRY4 delays
Eddie Hung
2019-05-24
1
-10
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+8
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-05-23
1
-0
/
+4
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Add "min bits" and "min wports" to xilinx dram rules
Eddie Hung
2019-05-23
1
-0
/
+4
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Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux
Eddie Hung
2019-05-23
1
-2
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+4
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Add "wreduce -keepdc", fixes #1016
Clifford Wolf
2019-05-20
1
-2
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+4
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Add whitebox support to DRAM
Eddie Hung
2019-05-23
5
-24
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+26
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shift register inference before mux
Eddie Hung
2019-05-22
1
-3
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+3
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Fix/workaround symptom unveiled by #1023
Eddie Hung
2019-05-21
1
-4
/
+14
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Instead of MUXCY/XORCY use CARRY4 (with timing)
Eddie Hung
2019-05-21
4
-11
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+20
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Modify LUT area cost to be same as old abc
Eddie Hung
2019-05-21
1
-10
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+9
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-05-21
5
-230
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+421
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ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
Sylvain Munaut
2019-05-13
1
-0
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+11
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Add "stat -tech xilinx"
Clifford Wolf
2019-05-11
1
-1
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+1
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Fix formatting for synth_intel.cc
Ben Widawsky
2019-05-09
1
-222
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+211
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Add "synth_xilinx -arch"
Clifford Wolf
2019-05-07
1
-1
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+13
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Merge remote-tracking branch 'origin/master' into clifford/specify
Eddie Hung
2019-05-03
6
-178
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+124
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Rename cells_map.v to prevent clash with ff_map.v
Eddie Hung
2019-05-03
1
-6
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+8
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Merge pull request #969 from YosysHQ/clifford/pmgenstuff
Clifford Wolf
2019-05-03
2
-0
/
+4
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Improve $specrule interface
Clifford Wolf
2019-04-23
1
-2
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+2
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Improve $specrule interface
Clifford Wolf
2019-04-23
1
-3
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+4
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Add $specrule cells for $setup/$hold/$skew specify rules
Clifford Wolf
2019-04-23
1
-0
/
+28
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Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...
Clifford Wolf
2019-04-23
1
-70
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+70
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Add $specify2 and $specify3 cells to simlib
Clifford Wolf
2019-04-23
1
-0
/
+147
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Trim off leading 1'bx in A
Eddie Hung
2019-05-02
1
-7
/
+20
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Add don't care optimisation
Eddie Hung
2019-05-02
1
-0
/
+11
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Use new peepopt from #969
Eddie Hung
2019-05-02
1
-10
/
+15
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Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux
Eddie Hung
2019-05-02
2
-0
/
+4
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Run "peepopt" in generic "synth" pass and "synth_ice40"
Clifford Wolf
2019-04-30
2
-0
/
+4
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Revert to pre-muxcover approach
Eddie Hung
2019-05-02
2
-25
/
+82
*
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Missing help_mode
Eddie Hung
2019-05-02
1
-1
/
+1
*
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Fix -nocarry
Eddie Hung
2019-05-02
1
-3
/
+3
*
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-05-02
5
-181
/
+123
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Back to passing all xc7srl tests!
Eddie Hung
2019-05-01
1
-5
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+4
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Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
Eddie Hung
2019-05-01
3
-170
/
+104
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Merge pull request #966 from YosysHQ/clifford/fix956
Clifford Wolf
2019-04-30
1
-1
/
+1
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Add handling of init attributes in "opt_expr -undriven"
Clifford Wolf
2019-04-30
1
-1
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+1
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Refactor synth_xilinx to auto-generate doc
Eddie Hung
2019-04-26
1
-153
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+95
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Cleanup ice40
Eddie Hung
2019-04-26
1
-4
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+6
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WIP
Eddie Hung
2019-04-28
1
-36
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+22
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Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung
2019-04-28
2
-9
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+12
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Revert synth_xilinx 'fine' label more to how it used to be...
Eddie Hung
2019-04-26
1
-21
/
+40
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Fix spacing
Eddie Hung
2019-04-26
1
-4
/
+4
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Apparently, this reduces number of MUXCY/XORCY
Eddie Hung
2019-04-26
1
-10
/
+9
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Try a different approach with 'muxcover'
Eddie Hung
2019-04-26
2
-88
/
+36
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