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* TypoEddie Hung2019-05-281-1/+1
* Make MUXF{7,8} and CARRY4 whiteboxEddie Hung2019-05-271-3/+3
* Re-enable lib_whiteboxEddie Hung2019-05-271-5/+5
* BlackboxesEddie Hung2019-05-262-10/+10
* Muck about with LUT delays some moreEddie Hung2019-05-261-5/+5
* Try new LUT delaysEddie Hung2019-05-241-8/+11
* Transpose CARRY4 delaysEddie Hung2019-05-241-10/+8
* Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-231-0/+4
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| * Add "min bits" and "min wports" to xilinx dram rulesEddie Hung2019-05-231-0/+4
* | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7muxEddie Hung2019-05-231-2/+4
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| * Add "wreduce -keepdc", fixes #1016Clifford Wolf2019-05-201-2/+4
* | Add whitebox support to DRAMEddie Hung2019-05-235-24/+26
* | shift register inference before muxEddie Hung2019-05-221-3/+3
* | Fix/workaround symptom unveiled by #1023Eddie Hung2019-05-211-4/+14
* | Instead of MUXCY/XORCY use CARRY4 (with timing)Eddie Hung2019-05-214-11/+20
* | Modify LUT area cost to be same as old abcEddie Hung2019-05-211-10/+9
* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-215-230/+421
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| * ice40/cells_sim.v: Add support for TRIM input to SB_HFOSCSylvain Munaut2019-05-131-0/+11
| * Add "stat -tech xilinx"Clifford Wolf2019-05-111-1/+1
| * Fix formatting for synth_intel.ccBen Widawsky2019-05-091-222/+211
| * Add "synth_xilinx -arch"Clifford Wolf2019-05-071-1/+13
| * Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-036-178/+124
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| | * Rename cells_map.v to prevent clash with ff_map.vEddie Hung2019-05-031-6/+8
| | * Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-032-0/+4
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| * | | Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
| * | | Improve $specrule interfaceClifford Wolf2019-04-231-3/+4
| * | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+28
| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...Clifford Wolf2019-04-231-70/+70
| * | | Add $specify2 and $specify3 cells to simlibClifford Wolf2019-04-231-0/+147
* | | | Trim off leading 1'bx in AEddie Hung2019-05-021-7/+20
* | | | Add don't care optimisationEddie Hung2019-05-021-0/+11
* | | | Use new peepopt from #969Eddie Hung2019-05-021-10/+15
* | | | Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7muxEddie Hung2019-05-022-0/+4
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| * | | Run "peepopt" in generic "synth" pass and "synth_ice40"Clifford Wolf2019-04-302-0/+4
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* | | Revert to pre-muxcover approachEddie Hung2019-05-022-25/+82
* | | Missing help_modeEddie Hung2019-05-021-1/+1
* | | Fix -nocarryEddie Hung2019-05-021-3/+3
* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-025-181/+123
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| * | Back to passing all xc7srl tests!Eddie Hung2019-05-011-5/+4
| * | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fineEddie Hung2019-05-013-170/+104
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| | * \ Merge pull request #966 from YosysHQ/clifford/fix956Clifford Wolf2019-04-301-1/+1
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| | | * | Add handling of init attributes in "opt_expr -undriven"Clifford Wolf2019-04-301-1/+1
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| | * | Refactor synth_xilinx to auto-generate docEddie Hung2019-04-261-153/+95
| | * | Cleanup ice40Eddie Hung2019-04-261-4/+6
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| * | WIPEddie Hung2019-04-281-36/+22
| * | Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-04-282-9/+12
| * | Revert synth_xilinx 'fine' label more to how it used to be...Eddie Hung2019-04-261-21/+40
* | | Fix spacingEddie Hung2019-04-261-4/+4
* | | Apparently, this reduces number of MUXCY/XORCYEddie Hung2019-04-261-10/+9
* | | Try a different approach with 'muxcover'Eddie Hung2019-04-262-88/+36
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