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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 16:19:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 16:19:45 -0700 |
| commit | ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c (patch) | |
| tree | 15c24a82884ffd0fabdd24ddfc48e2c16b08d583 /techlibs | |
| parent | 0f094fba08b69baa2329e749daf19f41a624a0a0 (diff) | |
| download | yosys-ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c.tar.gz yosys-ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c.tar.bz2 yosys-ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c.zip | |
Instead of MUXCY/XORCY use CARRY4 (with timing)
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc.box | 22 | ||||
| -rw-r--r-- | techlibs/xilinx/arith_map.v | 4 | ||||
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 3 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
4 files changed, 20 insertions, 11 deletions
diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box index d572817df..57ea1670c 100644 --- a/techlibs/xilinx/abc.box +++ b/techlibs/xilinx/abc.box @@ -1,5 +1,4 @@ -# Max delays from https://pastebin.com/v2hrcksd -# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321 +# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf # F7BMUX slower than F7AMUX # Inputs: I0 I1 S0 @@ -12,8 +11,17 @@ F7BMUX 1 1 3 1 MUXF8 2 1 3 1 104 94 273 -MUXCY 3 1 3 1 -1 1 1 - -XORCY 4 1 2 1 -1 1 +# CARRY4 + CARRY4_[ABCD]X +# Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 +# Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3 +CARRY4 3 1 10 8 +271 157 228 114 222 334 239 313 +536 494 592 580 482 598 584 642 +379 465 540 526 - 407 556 615 +- 445 520 507 - - 537 596 +- - 356 398 - - - 438 +- - - 385 - - - - +340 433 512 508 223 400 523 582 +- 469 548 528 - 205 558 618 +- - 292 376 - - 226 330 +- - - 380 - - - 227 diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index 09a5f07e8..5c848d4e6 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -180,7 +180,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); // First one if (i == 0) begin - CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_part + CARRY4 carry4_1st_part ( .CYINIT(CI), .CI (1'd0), @@ -207,7 +207,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); // First one if (i == 0) begin - CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_full + CARRY4 carry4_1st_full ( .CYINIT(CI), .CI (1'd0), diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 8b231480f..9db52b67a 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -155,7 +155,6 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5); assign O5 = I0 ? s5_1[1] : s5_1[0]; endmodule -(* abc_box_id = 3, lib_whitebox *) module MUXCY(output O, input CI, DI, S); assign O = S ? CI : DI; endmodule @@ -170,11 +169,11 @@ module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule -(* abc_box_id = 4, lib_whitebox *) module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule +(* abc_box_id = 3, lib_whitebox *) module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S); assign O = S ^ {CO[2:0], CI | CYINIT}; assign CO[0] = S[0] ? CI | CYINIT : DI[0]; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e9a3b53a0..ec7768ffe 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -261,6 +261,8 @@ struct SynthXilinxPass : public ScriptPass if (vpr && !nocarry && !help_mode) run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); + else if (abc == "abc9" && !nocarry && !help_mode) + run("techmap -map +/xilinx/arith_map.v -D _CLB_CARRY", "(skip if '-nocarry')"); else if (!nocarry || help_mode) run("techmap -map +/xilinx/arith_map.v", "(skip if '-nocarry')"); |