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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-26 19:46:34 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-26 19:46:34 -0700 |
| commit | 4aca928033874e8e35ecc4a18f22475c00bebad9 (patch) | |
| tree | 8d700e8582aff7aa46151fc068f5d3fc5289d5d0 /techlibs | |
| parent | 0f1ba949243aa7ccc7c6b42738a60a09be7a209e (diff) | |
| download | yosys-4aca928033874e8e35ecc4a18f22475c00bebad9.tar.gz yosys-4aca928033874e8e35ecc4a18f22475c00bebad9.tar.bz2 yosys-4aca928033874e8e35ecc4a18f22475c00bebad9.zip | |
Fix spacing
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 258b6c3de..6c280e0f1 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -147,7 +147,7 @@ module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y); input A, B, C, D, E, F, G, H, S, T, U; output Y; - wire [1:0] Z; + wire [1:0] Z; assign Z = T ? (S ? {D,H} : {C,G}) : (S ? {B,F} : {A,E}); MUXF7 fpga_muxf7 (.I0(Z[0]), .I1(Z[1]), .S(U), .O(Y)); @@ -157,9 +157,9 @@ module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y) input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V; output Y; - wire [1:0] Z; - \$_MUX8_ fpga_mux8_0 (.A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .S(S), .T(T), .U(U), .Y(Z[0])); - \$_MUX8_ fpga_mux8_1 (.A(I), .B(J), .C(K), .D(L), .E(M), .F(N), .G(O), .H(P), .S(S), .T(T), .U(U), .Y(Z[1])); + wire [1:0] Z; + \$_MUX8_ fpga_mux8_0 (.A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .S(S), .T(T), .U(U), .Y(Z[0])); + \$_MUX8_ fpga_mux8_1 (.A(I), .B(J), .C(K), .D(L), .E(M), .F(N), .G(O), .H(P), .S(S), .T(T), .U(U), .Y(Z[1])); MUXF8 fpga_muxf8 (.I0(Z[0]), .I1(Z[1]), .S(V), .O(Y)); endmodule `endif // NO_MUXFN |