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* Merge pull request #2585 from YosysHQ/dave/nexus-dotproductgatecat2021-02-121-0/+115
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| * nexus: Add MULTADDSUB9X9WIDE sim modelDavid Shah2020-12-081-0/+115
* | verilog: significant block scoping improvementsZachary Snow2021-01-315-81/+89
* | xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-271-3/+3
* | xilinx: Add FDRSE_1, FDCPE_1.Marcelina Kościelnicka2021-01-271-0/+80
* | Fix some trivial typos.Tom Verbeure2021-01-031-5/+5
* | Merge pull request #2480 from YosysHQ/dave/nexus-lramwhitequark2021-01-015-1/+227
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| * nexus: Add LRAM inferenceDavid Shah2020-12-075-1/+227
* | xilinx: Add some missing blackbox cells.Marcelina Kościelnicka2020-12-213-798/+6276
* | xilinx: Regenerate cells_xtra.v using Vivado 2020.2Marcelina Kościelnicka2020-12-212-42/+49
* | xilinx: Add FDDRCPE and FDDRRSE blackbox cells.Marcelina Kościelnicka2020-12-172-0/+33
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* nexus: More efficient CO mappingDavid Shah2020-12-021-2/+2
* add -noalu and -json option for apiculaPepijn de Vos2020-11-301-3/+32
* nexus: DSP inference supportDavid Shah2020-11-203-1/+117
* Merge pull request #2441 from YosysHQ/dave/nexus_dsp_simMiodrag Milanović2020-11-183-250/+573
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| * nexus: Add DSP simulation modelDavid Shah2020-11-183-250/+573
* | Fix duplicated parameter name typoMiodrag Milanovic2020-11-181-1/+1
* | synth_gowin: Add rPLL blackboxKonrad Beckmann2020-11-111-0/+45
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* nexus: Add make_transp to BRAMsDavid Shah2020-10-221-0/+3
* Merge pull request #2405 from byuccl/fix_xilinx_cellsclairexen2020-10-201-2/+2
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| * Move signal declarations to before first useJeff Goeders2020-10-191-2/+2
* | synth_nexus: Initial implementationDavid Shah2020-10-1514-0/+12229
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* xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)Eddie Hung2020-09-232-17/+65
* intel_alm: better map wide but shallow multipliesDan Ravensloft2020-08-281-2/+6
* intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-265-10/+103
* synth_intel: Remove incomplete Arria 10 GX support.Marcelina Kościelnicka2020-08-215-192/+4
* intel: move Cyclone V support to intel_almDan Ravensloft2020-08-207-203/+11
* Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixesclairexen2020-08-201-67/+35
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| * techmap/shift_shiftx: Remove the "shiftx2mux" special path.Marcelina Kościelnicka2020-08-201-67/+35
* | Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-patternclairexen2020-08-202-4/+4
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| * techmap: Add support for [] wildcards in techmap_celltype.Marcelina Kościelnicka2020-08-022-4/+4
* | Respect \A_SIGNED for $shiftXiretza2020-08-182-6/+16
* | intel_alm: fix typo in MISTRAL_MUL27X27 cell nameDan Ravensloft2020-08-131-1/+1
* | intel_alm: add more megafunctions. NFC.Dan Ravensloft2020-08-121-0/+431
* | Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-077-29/+26
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* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-312-2/+2
* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-304-142/+6
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-17/+12
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-277-39/+127
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-1/+1
* Merge pull request #2294 from Ravenslofty/intel_alm_timingsclairexen2020-07-234-72/+91
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| * intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-234-72/+91
* | Remove EXPLICIT_CARRY logic.Keith Rothman2020-07-233-150/+2
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* sf2: Emit CLKINT even if -clkbuf not passedMarcelina Kościelnicka2020-07-171-2/+6
* Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fixMiodrag Milanović2020-07-171-12/+12
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| * anlogic: Fix FF mapping.Marcelina Kościelnicka2020-07-171-12/+12
* | Merge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobsclairexen2020-07-164-214/+135
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| * sf2: replace sf2_iobs with {clkbuf,iopad}mapDan Ravensloft2020-07-094-214/+135
* | Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogicMiodrag Milanović2020-07-163-50/+35
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| * | anlogic: Use dfflegalize.Marcelina Kościelnicka2020-07-143-50/+35
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