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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-08-13 15:30:03 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-13 17:08:50 +0200 |
| commit | 3b534a203ae733c194415838259709dcf706c7bf (patch) | |
| tree | c192b5fb3ba786e2f84f6d8062c64198c6976c4b /techlibs | |
| parent | f61d62a7bc1d1acb6330106b6a1b8556a9098186 (diff) | |
| download | yosys-3b534a203ae733c194415838259709dcf706c7bf.tar.gz yosys-3b534a203ae733c194415838259709dcf706c7bf.tar.bz2 yosys-3b534a203ae733c194415838259709dcf706c7bf.zip | |
intel_alm: fix typo in MISTRAL_MUL27X27 cell name
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/intel_alm/common/dsp_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/intel_alm/common/dsp_sim.v b/techlibs/intel_alm/common/dsp_sim.v index 7e72dab0d..45fdebb3f 100644 --- a/techlibs/intel_alm/common/dsp_sim.v +++ b/techlibs/intel_alm/common/dsp_sim.v @@ -1,5 +1,5 @@ (* abc9_box *) -module MISTRAL_MUL27x27(input [26:0] A, input [26:0] B, output [53:0] Y); +module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y); // TODO: Cyclone 10 GX timings; the below are for Cyclone V specify |