| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Bump version | Yosys Bot | 2021-02-16 | 1 | -1/+1 |
| * | Merge pull request #2574 from dh73/master | Claire Xen | 2021-02-15 | 1 | -0/+5 |
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| | * | Accept disable case for SVA liveness properties. | Diego H | 2021-02-04 | 1 | -0/+5 |
| * | | Bump version | Yosys Bot | 2021-02-13 | 1 | -1/+1 |
| * | | Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct | gatecat | 2021-02-12 | 1 | -0/+115 |
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| | * | | nexus: Add MULTADDSUB9X9WIDE sim model | David Shah | 2020-12-08 | 1 | -0/+115 |
| * | | | Ganulate Verific support | Miodrag Milanovic | 2021-02-12 | 1 | -8/+16 |
| * | | | Bump version | Yosys Bot | 2021-02-12 | 1 | -1/+1 |
| * | | | Merge pull request #2573 from zachjs/repeat-call | whitequark | 2021-02-11 | 4 | -72/+176 |
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| | * | | | verilog: refactored constant function evaluation | Zachary Snow | 2021-02-04 | 4 | -72/+176 |
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| * | | | Merge pull request #2578 from zachjs/genblk-port | Zachary Snow | 2021-02-11 | 3 | -4/+29 |
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| | * | | | verlog: allow shadowing module ports within generate blocks | Zachary Snow | 2021-02-07 | 3 | -4/+29 |
| * | | | | Merge pull request #2584 from antmicro/atom_type_signedness | Zachary Snow | 2021-02-11 | 2 | -4/+23 |
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| | * | | | Add missing is_signed to type_atom | Kamil Rakoczy | 2021-02-11 | 2 | -4/+23 |
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| * | | | Bump version | Yosys Bot | 2021-02-07 | 1 | -1/+1 |
| * | | | Merge pull request #2576 from zachjs/port-bind-sign-uniop | whitequark | 2021-02-06 | 3 | -8/+33 |
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| | * | | | genrtlil: fix signed port connection codegen failures | Zachary Snow | 2021-02-05 | 3 | -8/+33 |
| * | | | | Bump version | Yosys Bot | 2021-02-06 | 1 | -1/+1 |
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| * | | | Merge pull request #2572 from antmicro/check-labels | whitequark | 2021-02-05 | 2 | -0/+28 |
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| | * | | | Add check of begin/end labels for genblock | Kamil Rakoczy | 2021-02-04 | 2 | -0/+28 |
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| * / / | Bump version | Yosys Bot | 2021-02-05 | 1 | -1/+1 |
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| * | | Merge pull request #2529 from zachjs/unnamed-genblk | whitequark | 2021-02-04 | 33 | -258/+779 |
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| | * | | verilog: significant block scoping improvements | Zachary Snow | 2021-01-31 | 33 | -258/+779 |
| * | | | Bump version | Yosys Bot | 2021-02-04 | 1 | -1/+1 |
| * | | | Merge pull request #2436 from dalance/fix_generate | whitequark | 2021-02-03 | 2 | -7/+4 |
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| | * | | | Fix begin/end in generate | dalance | 2020-11-11 | 2 | -7/+4 |
| * | | | | Bump version | Yosys Bot | 2021-01-31 | 1 | -1/+1 |
| * | | | | Require latest Verific build | Miodrag Milanovic | 2021-01-30 | 1 | -1/+1 |
| * | | | | Bump version | Yosys Bot | 2021-01-30 | 1 | -1/+1 |
| * | | | | ast: fix dump_vlog display of casex/casez | Marcelina Kościelnicka | 2021-01-29 | 1 | -2/+2 |
| * | | | | Merge pull request #2564 from whitequark/flatten-improve-error | whitequark | 2021-01-29 | 1 | -1/+1 |
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| | * | | | | flatten: clarify confusing error message. | whitequark | 2021-01-26 | 1 | -1/+1 |
| * | | | | | Bump version | Yosys Bot | 2021-01-29 | 1 | -1/+1 |
| * | | | | | Merge pull request #2569 from zachjs/macro-arg-surrounding-spaces | whitequark | 2021-01-28 | 2 | -1/+25 |
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| | * | | | | | verilog: strip leading and trailing spaces in macro args | Zachary Snow | 2021-01-28 | 2 | -1/+25 |
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| * | | | | | Merge pull request #2535 from Ravenslofty/scc-specify | Claire Xen | 2021-01-28 | 2 | -18/+61 |
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| | * | | | | scc: Add -specify option to find loops in boxes | Dan Ravensloft | 2021-01-26 | 2 | -18/+61 |
| * | | | | | Bump version | Yosys Bot | 2021-01-27 | 1 | -1/+1 |
| * | | | | | xilinx_dffopt: Don't crash on missing IS_*_INVERTED. | Marcelina Kościelnicka | 2021-01-27 | 3 | -4/+51 |
| * | | | | | xilinx: Add FDRSE_1, FDCPE_1. | Marcelina Kościelnicka | 2021-01-27 | 1 | -0/+80 |
| * | | | | | Merge pull request #2563 from whitequark/cxxrtl-msvc | whitequark | 2021-01-26 | 2 | -10/+10 |
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| | * | | | | | cxxrtl: do not use `->template` for non-dependent names. | whitequark | 2021-01-26 | 2 | -10/+10 |
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| * | | | | | Merge pull request #2544 from modwizcode/fix-clock | whitequark | 2021-01-26 | 1 | -7/+15 |
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| | * | | | | Improves the previous commit with a more complete coverage of the cases | Iris Johnson | 2021-01-15 | 1 | -12/+12 |
| | * | | | | Handle sliced bits as clock inputs (fixes #2542) | Iris Johnson | 2021-01-14 | 1 | -3/+11 |
| * | | | | | Bump version | Yosys Bot | 2021-01-26 | 1 | -1/+1 |
| * | | | | | Merge pull request #2549 from pgadfort/support-multiple-libs | whitequark | 2021-01-25 | 1 | -15/+21 |
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| | * | | | | | adding support for passing multiple liberty files to abc | Peter Gadfort | 2021-01-18 | 1 | -15/+21 |
| * | | | | | | Merge pull request #2550 from zachjs/macro-arg-spaces | whitequark | 2021-01-25 | 2 | -1/+28 |
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| | * | | | | | | verilog: allow spaces in macro arguments | Zachary Snow | 2021-01-20 | 2 | -1/+28 |
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