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* Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623Eddie Hung2020-01-172-119/+82
* +/xilinx/arith_map.v fix $lcu ruleEddie Hung2020-01-171-6/+6
* Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_WMiodrag Milanović2020-01-151-1/+1
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| * synth_xilinx: fix default W value for non-xc7Eddie Hung2020-01-141-1/+1
* | Merge pull request #1623 from YosysHQ/mmicko/edif_attrMiodrag Milanović2020-01-141-1/+1
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| * Use CARRY4 for abc1 as well, preventing issues with VivadoMiodrag Milanovic2020-01-101-1/+1
* | Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpadEddie Hung2020-01-131-4/+11
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| * | Another conflictEddie Hung2020-01-111-1/+0
| * | Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpadEddie Hung2020-01-111-2/+2
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| * | | synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macroEddie Hung2020-01-101-4/+11
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| * | Fix abc9_xc7.box commentsEddie Hung2020-01-071-7/+14
* | | synth_ice40: -abc2 to always use `abc` even if `-abc9`Eddie Hung2020-01-121-10/+10
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* | Fix abc9_xc7.box commentsEddie Hung2020-01-071-7/+14
* | Merge remote-tracking branch 'origin/master' into eddie/abc9_mfsEddie Hung2020-01-0713-220/+719
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| * Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2020-01-0613-217/+716
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| | * Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-065-1674/+509
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| | * \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-0619-40/+69
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| | * | | Fix spacingEddie Hung2020-01-021-1/+1
| | * | | synth_xilinx -dff to work with abc tooEddie Hung2020-01-021-6/+14
| | * | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-0214-66/+86
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| | * | | | Update commentsEddie Hung2020-01-021-11/+6
| | * | | | abc9 -keepff -> -dff; refactor dff operationsEddie Hung2020-01-022-58/+58
| | * | | | Clamp -46ps for FDPE* tooEddie Hung2020-01-011-2/+2
| | * | | | Restore abc9 -keepffEddie Hung2020-01-012-86/+6
| | * | | | Re-arrange FD orderEddie Hung2019-12-313-182/+182
| | * | | | Missing characterEddie Hung2019-12-311-1/+1
| | * | | | Cleanup xilinx boxesEddie Hung2019-12-312-391/+425
| | * | | | Cleanup ice40 boxesEddie Hung2019-12-313-30/+43
| | * | | | Cleanup ecp5 boxesEddie Hung2019-12-314-35/+31
| | * | | | Update abc9_xc7.box commentsEddie Hung2019-12-311-18/+18
| | * | | | FDCE ports to be alphabeticalEddie Hung2019-12-311-3/+3
| | * | | | Fix attributes on $__ABC9_ASYNC[01] whiteboxEddie Hung2019-12-311-2/+2
| | * | | | Fix incorrect $__ABC9_ASYNC[01] boxEddie Hung2019-12-311-2/+2
| | * | | | Do not offset FD* box timings due to -46ps TsuEddie Hung2019-12-301-12/+21
| | * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-3010-32/+377
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| | * | | | | Tidy up abc9_map.vEddie Hung2019-12-301-103/+103
| | * | | | | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-302-2/+98
| | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
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| | * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-204-172/+240
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| | * | | | | | | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-191-0/+78
| | * | | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-195-36/+55
| | * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1914-81/+995
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| | * \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1213-30/+32
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| | * | | | | | | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
| | * | | | | | | | | Fix commentEddie Hung2019-12-091-1/+1
| | * | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-067-745/+1138
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| | * | | | | | | | | | Remove creation of $abc9_control_wireEddie Hung2019-12-061-16/+6
| | * | | | | | | | | | abc9 to use mergeability class to differentiate sync/asyncEddie Hung2019-12-061-12/+15
| | * | | | | | | | | | Remove clkpartEddie Hung2019-12-051-4/+0
| | * | | | | | | | | | Revert "Special abc9_clock wire to contain only clock signal"Eddie Hung2019-12-051-10/+12